Prof. Dr. Wolfgang Rosenstiel Eberhard-Karls-Universität Tübingen Wilhelm-Schickard Institut für Informatik Lehrstuhl Technische Informatik Sand 13, B 207 72076 Tübingen Telefon: +49 (7071) 29-75482 Telefax: +49 (7071) 29-5062 E-Mail: rosenstiel Sprechstunde: Mittwoch: 12 - 14 Uhr, Einschränkungen wie folgt: Nächste Sprechstundentermine: 25.11. 13-14 Uhr; Freitag, den 11.12. 12-14 Uhr; (Ersatztermin) 23.12. 12-14 Uhr. Wenn Sie außerhalb dieser genannten Zeiten dringend einen Termin benötigen, dann können Sie sich an Frau Reimold wenden.

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 Alle Publikationen im BibTex-Format

Publikationen von 2009

• S. Eisenhardt, T. Schweizer, A. Bernauer, T. Kuhn, W. Rosenstiel
   Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures
  International Conference on ReConFigurable Computing and FPGAs (ReConFig), to be published, IEEE, Cancun, Mexico

• J.Oliveira Filho, S. Masekowsky, T. Schweizer, W.Rosenstiel
   CGADL: an Architecture Description Language for Coarse-Grained Reconfigurable Arrays
  IEEE Transactions in Very Large Scale Integration Systems
• A. Bernauer, O. Bringmann, W. Rosenstiel
    Generic Self-Adaptation to Reduce Design Effort for System-on-Chip
  IEEE International Conference on Self-Adaptive and Self-Organizing Systems, p.126-135, San Francisco
• S. P. Subramanian, J. Sommer, S. Schmitt, W. Rosenstiel
   INR –Indoor Navigator with RFID Locator
  Third International Conference and Exhibition on Next Generation Mobile Applications,Services and Technologies (NGMAST 2009), IEEE Computer Society Press, Cardiff, UK.
• S. P. Subramanian, J. Sommer, F. Zeh, S. Schmitt, W. Rosenstiel
   PBIL - PDR for scalable Bluetooth Indoor Localization
  Third International Conference and Exhibition on Next Generation Mobile Applications,Services and Technologies (NGMAST 2009), IEEE Computer Society Press, Cardiff, UK.
• J. Sommer, S. Lüders, S. Subramanian, S. Schmitt, W. Rosenstiel
   SySifoS – SystemC Simulator for Sensor and Communication Systems
  ACM Mobility Conference (ACMMOBILITY 2009). The international conference on Mobile Technology, Applications and Systems. 2 - 4 september 2009, Nice, France.

• S. Lämmermann, M. Rathgeber, A. Jesser, J. Ruf, L. Hedrich, T. Kropf, W. Rosenstiel
   Checking Heterogeneous Signal Characteristics: Applying Assertion-Based Verification
  Formal Verification of Analog Circuits at CAV'09 (FAC) , Grenoble, France

• S. Lämmermann, A. Jesser, R. Weiss, J. Ruf, L. Hedrich, T. Kropf, W. Rosenstiel
   An Assertion-Based Verification Methodology for SystemC-AMS Designs
  15th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), p.434-435, Okinawa, Japan
• S. Eisenhardt, J. Oliveira, T. Kuhn, W. Rosenstiel
   Speculative Configuration Prefetching for Multi-Context Architectures
  Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Okinawa, Japan

Publikationen von 2008

• A. Jesser, S. Laemmermann, A. Pacholik, R. Weiss, J. Ruf, W. Fengler, L. Hedrich, T. Kropf, W. Rosenstiel
    Advanced Assertion Based Design for Mixed-Signal Verification
  IEICE TRANS. FUNDAMENTALS: Special Section on VLSI Design and CAD Algorithms, Vol.E91–A(12), p.3548-3555
• Oliveira, Kuhn, Rosenstiel
   Evaluating the Impact of Customized Instruction Set on Coarse Grained Reconfigurable Arrays
  Proceedings of the International Conference on Field-Programmable Technology (ICFPT), Taiwan
• S. Eisenhardt, T. Oppold, T. Schweizer, W. Rosenstiel
   Optimizing Partial Reconfiguration of Multi-Context Architectures
  International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, Cancun, Mexico

• Andreas Bernauer, Dirk Fritz, Wolfgang Rosenstiel
   Evaluation of the Learning Classifier System XCS for SoC run-time control
  Lecture Notes in Informatics, Vol.134, p.761-768, Springer, Gesellschaft für Informatik
• Stefan Lämmermann, Alexander Pacholik, Alexander Jesser, Roland Weiss, Jürgen Ruf, Wolfgang Fengler, Lars Hedrich, Thomas Kropf, Wolfgang Rosenstiel
   Improving Mixed-Signal Verification by Assertion Based Design
  16th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), p.144-148, Rhodos, Griechenland

• M. Bensch, J. Mellinger, M. Bogdan, W. Rosenstiel
    A Multiclass BCI using MEG
  Proceedings of the 4th Int. Brain-Computer Interface Workshop, p.191-196, Graz
• P. Heckeler, M. Ritt, J. Behrend, W. Rosenstiel
   Object-oriented message-passing in heterogeneous environments
  EuroPVM/MPI 2008, p.151-158, Springer LNCS, Dublin

• Bartholomä, Greiner, Kesel, Rosenstiel
   A Systematic Approach for Synthesizing VLSI Architectures of Lifting-Based Filter Banks and Transforms
  IEEE Transactions on Circuits and Systems, Vol.55(7)
• Bartholomä, Greiner, Kesel, Rosenstiel
   A Systematic Approach for Synthesizing VLSI Architectures of Lifting-Based Filter Banks and Transforms
  IEEE Transactions on Circuits and Systems, Regular Papers, Vol.55(7)

• J. OliveiraFilho, A. Bunoza, J. Sommer, W. Rosenstiel
   Self-Localization in a Low Cost Bluetooth Environment
  Lecture Notes in Computes Science, Vol.5061, Oslo

• M. Müller, J. Gerlach, W. Rosenstiel
   Abstrakte Modellierung von Hardware/Software-Systemen unter Berücksichtigung von RTOS-Funktionalität
  11. GI/ITG/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Freiburg
• D. Brugger, M. Bogdan, W. Rosenstiel
   Automatic Cluster Detection in Kohonen's SOM
  IEEE Transactions on Neural Networks, Vol.19(3)

• Bartholomä, Greiner, Kesel, Rosenstiel
   Automatic Synthesis of VLSI Architectures for Arbitrary Lifting-Based Filter Banks and Transforms
  IEEE International Conference on Acoustics, Speech, and Signal Processing
• Bartholomä, Greiner, Kesel, Rosenstiel
   Automatic Synthesis of VLSI Architectures for Arbitrary Lifting-Based Filter Banks and Transforms
  IEEE International Conference on Acoustics, Speech, and Signal Processing
• E. Mugler, M. Bensch, S. Halder, W. Rosenstiel, M. Bogdan, N. Birbaumer, A. Kübler
    Control of an Internet Browser Using the P300 Event Related Potential
  International Journal of Bioelectromagnetism, Vol.10(1), p.56-63
• Andreas Bernauer, Dirk Fritz, Björn Sander, Oliver Bringmann, Wolfgang Rosenstiel
    Current state of ASoC design methodology
  Organic Computing - Controlled Self-organization, Nr.08141, Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik, Dagstuhl, Germany, ISSN 1862-4405
• Brugger, Butovas, Bogdan, Schwarz, Rosenstiel
   Direct and inverse solution for a stimulus adaptation problem using SVR
  ESANN Proceedings , p.397-402
• Brugger, Butovas, Bogdan, Schwarz, Rosenstiel
   Direct and inverse solution for a stimulus adaptation problem using SVR
  ESANN Proceedings , p.397-402
• Schnerr, Bringmann, Viehl, Rosenstiel
   High-Performance Timing Simulation of Embedded Software
  45th Design Automation Conference (DAC), Anaheim
• Viehl, Sander, Bringmann, Rosenstiel
   Integrated Requirement Evaluation of Non-Functional System-on-Chip Properties
  Forum on specification & Design Languages (FDL), Stuttgart
• T. Schairer, C. Weiss, P. Vorst, J. Sommer, C. Hoene, W. Rosenstiel, W. Straßer, A. Zell, P. Schneider, A. Weisbecker, G. Carle
   Integrated Scenario for Machine-Aided Inventory Using Ambient Sensors
  4. European Workshop on RFID Systems and Technologies (RFID SysTech), Freiburg
• Mielenz, Graf, Dölling, Gerlach, Rosenstiel
   Microcontroller Embedding of support Vector Machines and its Application to Signal Processing for Smart Sensor Systems
  edaWorkshop
• Mielenz, Graf, Dölling, Gerlach, Rosenstiel
   Microcontroller Embedding of support Vector Machines and its Application to Signal Processing for Smart Sensor Systems
  Signal Processing for Smart Sensor Systems edaWorkshop
• Viehl, Sander, Bringmann, Yang, Rosenstiel
   Quantitative Bewertung nicht-funktionaler Systemanforderungen von System-on-Chip-Entwürfen
  DASS, Dresden
• Graf, Mielenz, Gerlach, Rosenstiel
   Software based adaptation of a non dispersive infrared sensor for surface Classification
  Eurosensors, Dresden
• Lettnin, Nalla, Ruf, Kropf, Rosenstiel, Kirsten, Schönknecht, Reitemeyer
   Verification of Temporal Properties in Automotive Embedded Software.
  In: Design, Automation and Test in Europe

Publikationen von 2007

• J. O. Filho, S. Masekowsky, T. Schweizer, W. Rosenstiel
    An Architecture Description Language for coarse-grained Reconfigurable Arrays
  International Conference on Hardware/Software Codesign and System Synthesis (CODES) - Workshop on Application Specific Processors (WASP), Salzburg, Austria
• A. Jesser, S. Lämmermann, A. Pacholik, R. Weiss, J. Ruf, W. Fengler, L. Hedrich, T. Kropf, W. Rosenstiel
   Analog Simulation Meets Digital Verification - A Formal Assertion Approach for Mixed-Signal Verification
  14. Workshop on Synthesis And System Integration of Mixed Information technologies (SASIM), p.507-514, Sapporo, Japan
• P. Heckeler, J. Behrend, H. Planatscher, W. Rosenstiel
   Grid-Middlewares für Campus Grids
  Grid-Technologie für den Entwurf technischer Systeme, Dresden

• J. Behrend, A. Braun, O. Bringmann, M. Krause, T. Kropf, S. Lämmermann, P. Nalla, W. Rosenstiel, J. Ruf, T. Schönwald, A. Viehl u. J. Zimmermann
    Entwurf und Verifikation von Hardware/Software - Systemen
  Kooperationsmarkt des Ekompass-Workshops, Hannover, Germany

• S. Lämmermann, J. Behrend, R. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
   UML/SysML-Systemanalyse zur Generierung von formalen Verifikationseigenschaften für verschiedene Abstraktionsebenen
  Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), p.29-38, Erlangen, Germany

• D. Lettnin, M. Winterholer, A. Braun, J. Gerlach, J. Ruf, T. Kropf, W. Rosenstiel
   Coverage Driven Verification applied to Embedded Software
  IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Porto Alegre, Brazil
• T. Oppold, T. Schweizer, J. F. Oliveira, S. Eisenhardt, W. Rosenstiel
     CRC - Concepts and Evaluation of Processor-Like Reconfigurable Archtitectures
  it - Information Technology, DOI: 10. 1524/itit, 49. 3. 157, Vol.49(3)
• M. Rullmann, S. Siegel, R. Merker, J. O. Filho, T. Schweizer, T. Oppold, W. Rosenstiel
    Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable Architecture
  20. International Conference on Architecture of Computing Systems (ARCS), Workshop on Dynamically Reconfigurable Systems (DRS), Zürich, Schweiz
• T. Schweizer, T. Oppold, J. O. Filho, S. Eisenhardt, K. Blocher, W. Rosenstiel
    Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures
  International Conference on Field Programmable Technology (ICFPT), Kitakyushu, Japan
• P. K. Nalla, J. Behrend, P. M. Peranandam, J. Ruf, T. Kropf, W. Rosenstiel
   Grid Based Fast Falsification For Bounded Property Checking
  Forum on Specification & Design Languages (FDL)
• M. Bensch, A. Karim, J. Mellinger, T. Hinterberger, M. Tangermann, M. Bogdan, W. Rosenstiel, N. Birbaumer
    Nessi: An EEG controlled web browser for severely paralyzed patients
  Computational Intelligence and Neuroscience
• S. Halder, M. Bensch, J. Mellinger, M. Bogdan, A. Kübler, N. Birbaumer, W. Rosenstiel
    Online Artifact Removal for Brain-Computer Interfaces Using Support Vector Machines and Blind Source Separation
  Computational Intelligence and Neuroscience, DOI:10.1155/82069, Nr.82069, p.10
• T. Oppold, S. Eisenhardt, W. Rosenstiel
    Optimization of Area and Performance by Processor-Like Reconfiguration
  International Parallel and Distributed Processing Symposium (IPDPS) - Reconfigurable Architectures Workshop (RAW), Long Beach, USA
• S. Waldert, M. Bensch, M. Bogdan, W. Rosenstiel, B. Schölkopf, C. Lowery, H. Eswaran, H. Preissl
    Real-Time Fetal Heart Monitoring in Biomagnetic Measurements Using Adaptive Real-Time ICA
  IEEE Transactions on Biomedical Engineering, Vol.54(10), p.1867-1874
• M. Bensch, D. Brugger, P. Baeuerle, W. Rosenstiel, M. Bogdan, W. Spruth
   Self-Learning Prediciton System for Optimisation of Workload Managememt in a Mainframe Operating System
  International Conference on Enterprise Information Systems, Funchal
• D. Lettnin, P. Nalla, J. R. R. Wess, A. Braun, J. Gerlach, T. K. a. W. Rosenstiel
   Semiformal Verification of Temperal Properties in Embedded Software
  10. Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Erlangen, Germany

Publikationen von 2006

• A. Bouajila, J. Zeppenfeld, W. Stechele, A. Herkersdorf, A. Bernauer, O. Bringmann, W. Rosenstiel
    Organic Computing at the System on Chip Level
  In Proceedings of the IFIP International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC), Springer

• A. Bernauer, O. Bringmann, W. Rosenstiel, A. Bouajila, W. Stechele, A. Herkersdorf
    An Architecture for Runtime Evaluation of SoC Reliability
  In INFORMATIK - Informatik für Menschen, GI-Edition - Lecture Notes in Informatics, Vol.93, p.177-185, Kölle Verlag, Bonn
• M. Bensch, M. Bogdan, W. Rosenstiel
    Phase Synchronization in MEG for Brain-Computer Interfaces
  In Proceedings of the 3rd Int. Brain-Computer Interface Workshop, p.18-19, Graz
• J. O. Filho, T. Schweizer, T. Oppold, T. Kuhn, W. Rosenstiel,
    Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain
  3. International Conference on Reconfigurable Computing and FPGAs (ReConfig), p.71-77, San Luis Potosi, Mexiko

• A. Bouajila, A. Bernauer, A. Herkersdorf, W. Rosenstiel, O. Bringmann, W. Stechele
    Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoC
  In Yi Pan, Franz J. Rammig, Hartmut Schmeck, and Mauricio Solar, editors, 1st IFIP International Conference on Biologically Inspired Cooperative Computing (BICC), Vol.216(107-113), Springer, Boston, MA, USA

• S. Lämmermann, R. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
    Automatic Generation of Verification Properties for SoC Design from SysML-Diagrams
  3rd Inernational UML for SoC Design Workshop at DAC'06 (UML-SoC), p.29-34, San Francisco, USA

• G. Lipsa, A. Herkersdorf, W. Rosenstiel, O. Bringmann, W. Stechele.
    Towards a Framework and a Design Methodology for Autonomic SoC
  In 2nd IEEE International Conference on Autonomic Computing, Seattle, USA

• P. K. Nalla, P. M. Peranandam, J. Ruf, S. Laemmermann, J. Behrend, R. Weiss, T. Kropf, W. Rosenstiel
    Fast Distributed Property Checking
  Design Automation and Test in Europe (DATE), University Booth

• S. Lämmermann, R. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
   Automatische Eigenschaftsextraktion auf Systemebene aus SystemC Modellen
  Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), p.222-226, Dresden, Germany

• M. Krause, O. Bringmann, W. Rosenstiel
   A SystemC-based Software and Communication Refinement Framework for Distributed Embedded Systems
  13. Workshop on Synthesis And System Integration of Mixed Information Technologies, Nagoya, Japan
• M. Krause, O. Bringmann, W. Rosenstiel
   Communication Refinement and Target Software Generation using SystemC
  GI/ITG/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Dresden
• T. Oppold, S. Eisenhardt, W. Rosenstiel
    Design and Validation of Execution Schemes for Dynamically Reconfigurable Architectures
  International Conference on Field Programmable Technology (FPT), Bangkok, Thailand
• E. Sapozhnikova, M. Bogdan, B. Speiser, W. Rosenstiel
   EChem++ - An Object-Oriented Problem Solving Environment for Electrochemistry. 3. Classification of voltammetric signals by the Fuzzy ARTMAP neural network with respect to reaction mechanisms
  Journal of Electroanalytical Chemistry, Vol.588
• T. Oppold, W. Rosenstiel
    Evaluation and Design of Processor-Like Reconfigurable Architectures
  International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain
• T. Oppold, T. Schweizer, J. F. Oliveira, S. Eisenhardt, T. Kuhn, W. Rosenstiel
    Execution Schemes for Dynamically Reconfigurable Architectures
  Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Nagoya, Japan
• P. M. Peranandam, P. K. Nalla, J. Ruf, R. J. Weiss, T. Kropf, W. Rosenstiel
   Fast Falsification Based on Symbolic Bounded Property Checking
  43rd Design Automation Conference (DAC)
• J. H. Oetjens, J. Gerlach, W. Rosenstiel
   Flexible Specification and Application of Rule-Based Transormations in an Automotive Design Flow
  Proceedings of Design, Automation and Test in Europe (DATE)
• A. Viehl, T. Schönwald, O. Bringmann, W. Rosenstiel
   Formal Performance Analysis and Simulation of UML/SysML Models for ESL Design
  DATE
• P. Duplys, R. J. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
   Monitoring-based Formal Hardware Verification
  Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV)
• J. A. Brenner, J. C. v. d. Veen, S. P. Fekete, J. O. Filho, W. Rosenstiel
    Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures
  Proceedings of the 17. International Conference on Field Programmable Logic and Applications, Spanien
• Ruf, J., Weiss, R., Lettnin, D. V., Lämmermann, S., Kropf, T., Rosenstiel, W.
   SystemC Temporal Checker
  Tübingen: Department of Computer Engineering
• A. Herkersdorf, W. Rosenstiel
    Towards a Framework and a Design Methodology for Autonomic Integrated System
  In Proceedings Dynamically Reconfigurable Systems Self-Organization and Emergence, Architecture of Computing Systems (ARCS), p.101-108
• A. Viehl, O. Bringmann, W. Rosenstiel
   Virtual Prototyping und frühe Evaluierung von Systems-on-Chip mit UML2 und SysML
  In Proceeding of GI/ITG/GMM Workshop für Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Dresden, Germany

Publikationen von 2005

• A. Viehl, O. Bringmann, W. Rosenstiel
   Performance Analysis of Sequence Diagrams for SoC Design
  In Proceedings of the 2nd UML for SoC-Design Workshop (UML-SoC), 42nd Design Automation Conference (DAC), p.55-61, Anaheim
• Bensch, Schröder, Bogdan, Rosenstiel, Hinterberger, Mellinger, Birbaumer
    The Web Browser "Nessi" - A BCI Application
  3rd International BCI meeting, Albany, USA

• M. Bensch, M. Schröder, M. Bogdan, W. Rosenstiel
      Feature Selection for High-Dimensional Industrial Data
  ESANN, Brugge
• M. Bensch, M. Schröder, M. Bogdan, W. Rosenstiel, P. Czerner, R. Montino, G. Soberger, P. Linke, R. Schmidt
   Neural network algorithms for generalised online tool control in medium size semiconductor fabs
  European Advanced Equipment Control/Advanced Process Control (AEC/APC) Konferenz

• P. K. Nalla, P. M. Peranandam, J. Ruf, R. Weiss, T. Kropf, W. Rosenstiel
   Bounded Property Checking with SymC
  Design Automation and Test in Europe (DATE), University Booth

• T. M. Lal, M. Schröder, N. J. Hill, H. Preissl, T. Hinterberger, J. Mellinger, M. Bogdan, W. Rosenstiel, T. Hoffmann, N. Birbaumer, B. Schölkopf
   A Brain Computer Interface with Online Feedback based on Magnetoencephalography
  Int. Conf. on Machine Learning ICML, Bonn
• T.Hermle, M. Bogdan, C. Schwarz, W. Rosenstiel
   ANN-based System for Sorting Spike Waveforms Employing Refractory Periods
  ICANN, Warszawa
• A. Siebenborn, O. Bringmann, W. Rosenstiel
   Conflict Analysis in Multiprocess Synthesis for Optimized System Integration
  International Conference on Hardware - Software Co-Design and System Synthesis, CODES+ISSS
• J. Schnerr, O. Bringmann, W. Rosenstiel
   Cycle Accurate Binary Tanslation for Simulation Acceleration in Rapid Prototyping of SoCs
  In Proceedings of Design, Automation and Test in Europe (DATE)
• R. J. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
   Efficient and customizable integration of temporal properties into systemc
  Forum on Specification and Design Languages (FDL)
• L. S. Avila, D. Dölling, W. Rosenstiel
   Eine teilautomatisierbare Methodik für den Übergang von der System- auf die Schaltungsebene am Beispiel eines Reglerentwurfs aus dem Automobilbereich
  In Proceedings of Analog
• T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel, U. Kanus, W. Straßer
    Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures
  International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland
• T. Schweizer, J. F. Oliveira, T. Oppold, T. Kuhn, W. Rosenstiel
    Evaluation of Temporal-Spatial Voltage Scaling for Processor-Like Reconfigurable Architectures
  Euro DesignCon, Munich, Germany
• S. Schmitt, W. Rosenstiel
   Fast and efficient development of hardware-dependent software for SoC designs
  Proceedings of the Euro DesignCon
• P. Lysaght, W. Rosenstiel
   New Algorithms, Architectures and Applications for Reconfigurable Computing
  Springer Verlag
• P. M. Peranandam, P. K. Nalla, R. J. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
   Overlap reduction in symbolic system traversal
  IEEE International High Level Design Validation and Test Workshop (HLDVT)
• P. K. Nalla, R. J. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
   Parallel bounded property checking with SymC
  Modellierung und Verifikation, 8. GI/ITG/GMM Workshop
• W. Qin, S. Pinkenburg, W. Rosenstiel
   Parallel Motif Search Using PARSEQ
  In Proceedings of the International Conference on Parallel and Distributed Computing and Networks (PDCN)
• M. Schröder, T. M. Lal, T. Hinterberger, M. Bogdan, N. J. Hill, N. Birbaumer, W. Rosenstiel, B. Schölkopf
   Robust EEG Channel Selection Across Subjects for Brain Computer Interfaces
  EURASIP Journal on Applied Signal Processing, Special Issue: Trends in Brain Computer Interfaces, Vol.19
• P. K. Nalla, R. J. Weiss, P. Peranandam, J. Ruf, T. Kropf, W. Rosenstiel
   Symbolic bounded property checking in parallel
  In 4th International Workshop on Parallel and Distributed Methods in Verification, Electronic Notes in Theoretical Computer Science, Elsevier
• R. J. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
   Symbolic model checking and simulation with temporal assertions
  Advances in Design and Specification Languages for SoCs, Springer
• R. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
   Symbolic model checking and simulation with temporal assertions
  In Proceedings of Design, Automation and Test in Europe (DATE)
• D. Lettnin, R. Weiss, A. Braun, J. Ruf, W. Rosenstiel
   Temporal Properties Verification of System Level Design
  In: Workshop on Object Oriented Software Design for Real Time and Embedded Computer Systems, 2005, Erfurt. Proceedings Net.ObjectDays 2005., p.271-282
• L. S. Avila, D. Dölling, W. Rosenstiel
   Towards seamless top-down design of A/MS systems: An example of system to block-level design in automotive applications
  In Proceedings of Forum on Design Languages (FDL)

Publikationen von 2004

• A. Herkersdorf, W. Rosenstiel
    Towards a Framework and a Design Methodology for Autonomic Integrated System
  In INFORMATIK - GI Workshop on Organic Computing, p.610-615, Ulm, Germany

• T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel
    A Design Environment for Processor-Like Reconfigurable Hardware
  IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC), Dresden, Germany
• T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel
    A New Design Approach for Processor-Like Reconfigurable Hardware
  Euro DesignCon, München
• A. Vörg, W. Rosenstiel
   Automation of IP qualification and IP exchange
  The VLSI journal, Vol.37
• A. Siebenborn, O. Bringmann, W. Rosenstiel
   Communication Analysis for System on Chip Design
  In Proceedings of Design, Automation and Test in Europe (DATE)
• T. Oppold, T. Schweizer, T. Kuhn, W. Rosenstiel
    Cost Functions for the Design of Dynamically Reconfigurable Processor Architectures
  Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Kanazawa, Japan
• P. M. Peranandam, R. J. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
   Dynamic guiding of bounded property checking
  In IEEE International High Level Design Validation and Test Workshop (HLDVT)
• J. H. Oetjens, J. Gerlach, W. Rosenstiel
   Ein XML-basierter Ansatz zur flexiblen Darstellung und Transformation von Schaltungsbeschreibungen, Modellierung und Beschreibungssprachen
  In Proceedings of GI/ITG/GMM Workshop
• W. Rosenstiel
   IP and design reuse
  The VLSI journal, Vol.37
• A. Vörg, M. Radetzki, W. Rosenstiel
   Measurement of IP Qualification Costs and Benefits
  In Proceedings of Design, Automation and Test in Europe (DATE)
• T. N. Lal, T. Hinterberger, G. Widman, M. Schröder, J. Hill, W.Rosenstiel, C. E. Elger, B. Schölkopf, N. Birbaumer
   Methods Towards Invasive Human Brain Computer Interfaces
  NIPS
• J. Ruf, R. J. Weiss, T. Kropf, W. Rosenstiel
   Modeling and formal verification of production automation systems
  Integration of Software Specification Techniques for Applications in Engineering, Lecture Notes in Computer Science, Vol.3147, p.541-566, Springer
• J. Ruf, R. Weiss, T. Kropf, W. Rosenstiel
   Modeling and Formal Verification of Production Automation Systems
  In Proceedings of Forum on Design Languages (FDL)
• M. Winterholer, C. Schulz-Key, T. Schweizer, T. Kuhn, W. Rosenstiel
   Object-Oriented Hardware Synthesis with SystemC
  In Proceedings of Forum on Design Languages (FDL)
• C. Schulz-Key, M. Winterholer, T. Schweizer, T. Kuhn, , W. Rosenstiel
    Object-Oriented Modeling and Synthesis of SystemC Specifications
  Asia South Pacific Design Automation Conference (ASPDAC), Yokohama, Japan
• M. Hipp, W. Rosenstiel
   Parallel Hybrid Particle Simulations Using MPI and OpenMP
  In Proceedings of Euro-Par, Parallel Processing, 10th International Euro-Par Conference
• S. Pinkenburg, W. Rosenstiel
   Parallel I/O in an object-oriented message-passing library
  Recent Advances in Parallel Virtual Machine and Message Passing Interface (PVM/MPI), Springer
• S. Schmitt, W. Rosenstiel
   Rapid Prototyping of a Microcontroller IP Core under Resource Limitations
  In Lindwer, Gerousis, Figueras (Eds.): Design, Automation and Test in Europe (DATE), Designers Forum, Paris
• D. Lettnin, A. Braun, M. Bogdan, J. Gerlach, W. Rosenstiel
   Synthesis of SystemC Design: A Case Study of Digital Neural Networks
  In: Design, Automation and Test in Europe (DATE 04), Paris
• D. Sciuto, H. Martin, R. Swan, O. Flake, F. Ghenassia, J. Srouji, W. Rosenstiel
   SystemC and SystemVerilog: Where do they fit? Where are they going?
  In Proceedings of Design, Automation and Test in Europe (DATE)
• A. Herkersdorf, W. Rosenstiel
   Towards a Framework and a Design Methodology for Autonomic Integrated Systems
  GI-Edition Lecture Notes in Informatics, Informatik – Informatik verbindet, Beiträge der 34. Jahrestagung der Gesellschaft für Informatik e.V, Vol.2
• S. Schmitt, W. Rosenstiel
   Verification of a Microcontroller IP Core for System-on-Chip Designs Using Low-Cost Prototyping Environments
  In: Stoffel, Kunz (Eds.): Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Kaiserslautern

Publikationen von 2003

• E. Sapozhnikova, W. Rosenstiel
   AFC: ART-based Fuzzy Classifier
  In Proceedings of KES, p.30-36, Oxford, United Kingdom

• U. Stark, A. Braun, W. Rosenstiel
   A Flexible Methodology for the XML-based Automated Interface Generation in Co-Simulation Environments
  Dresdner Arbeitstagung Schaltungs- und Systementwurf (DASS), Workshop System Design Automation (SDA)
• E. Sapozhnikova, W. Rosenstiel
   AFC: ART-Based Fuzzy Classifier Knowledge-Based Intelligent Information and Engineering Systems
  Proceedings of 7th International Conference, KES, Part II
• M. Bogdan, M. Schröder, W. Rosenstiel
   Artificial Neural Net Based Signal Processing for Interaction with Peripheral Nervous System
  1st Int. IEEE EMBS Conf. on Neural Engineering, Capri
• A. Braun, J. Freuer, J. Gerlach, W. Rosenstiel
   Automated Conversion of SystemC Fixed-Point Data Types for Hardware Synthesis
  IFIP VLSI-SoC
• M. Schröder, M. Bogdan, W. Rosenstiel, T. Hinterberger, N. Birbaumer
   Automated EEG Feature Selection for Brain Computer Interfaces
  1st Int. IEEE EMBS Conf. on Neural Engineering, Capri
• J. Ruf, P. M. Peranandam, T. Kropf, W. Rosenstiel
   Bounded property checking with symbolic simulation (2)
  In Forum on Specification and Design Languages
• A. Braun, E. Schubert, U. Stark, U. Haug, J. Gerlach, W. Rosenstiel
   Case Study: SystemC-Based Design of an Industrial Exposure Control Unit
  Proceedings of Forum on Specification & Design Languages (FDL)
• J. Schnerr, U. Haug, W. Rosenstiel
   Instruction Set Emulation for Rapid Prototyping of SoCs
  Proceedings of Design, Automation and Test in Europe (DATE)
• W. Rosenstiel
   Modelling, Verification, and Synthesis with SystemC - Principles and Examples
  Medea and Design Automation Conference
• W. Rosenstiel
   Moderne Prozessoren
  Symposium Tendenzen der Informationstechnik, IBM Herrenberg
• M. Müller, W. Rosenstiel, J. Ruf
   SystemC - Methodologies and Applications
  , Kluwer Academic Publishers
• M. Bogdan, M. Schröder, W. Rosenstiel
   Towards the Restoration of Hand Grasp Function of Quadripledgic Patients based on an Artificial Neural Net Controller - an Approach
  ESANN, Brugge
• M. Bogdan, M. Schröder, W. Rosenstiel
   Towards the Restoration of Hand Grasp Function of Quadriplegic Patients based on Artificial Neural Net Controller using Peripheral Nerve Stimulation - an Approach
  ESANN, p.427-432, Brugge
• W. Rosenstiel
   Transaction Level Modeling in SystemC
  Summer School Multiprocessor System on Chip
• J. Ruf, P. Peranandam, T. Kropf, W. Rosenstiel
   Using Symbolic Simulation for Bounded Property Checking
  Proceedings of Forum on Design Languages (FDL)

Publikationen von 2002

• R. Seepold, A. H. G. Martinez, A. Vörg, W. Rosenstiel, Radetzki, U. Neumann, J. Haase
   A Qualification Platform for Design Reuse
  International Symposium for Quality Electronic Design
• R. Seepold, A. H. G. Martinez, A. Vörg, W. Rosenstiel, Radetzki, U. Neumann, J. Haase
   A Qualification Platform for Design Reuse
  International Symposium for Quality Electronic Design (ISQED)
• A. Braun, J. Gerlach, W. Rosenstiel
   Checking Temporal Properties in SystemC Specifications
  In Proceedings of High Level Design Validation and Test Workshop (HLDVT)
• C. Menn, O. Bringmann, W. Rosenstiel
   Controller Estimation for FPGA Target Architectures during High-Level Synthesis
  15th International Symposium on System Synthesis (ISSS), IEEE Computer Society Press
• T. Oppold, W. Rosenstiel
    IP Design for Dynamically Reconfigurable SoCs
  International Workshop on IP-Based SoC Design, Grenoble, Frankreich
• F. Höhn, T. Hermle, H. A. Mayer, E. Lindner, W. Rosenstiel
   Neural Networks Evaluating NMR Data: An Approach to Visualize Similarities and Relationships of Sol-Gel Derived Inorganic-Organic And Organometallic Hybrid Polymers
  J. Chem. Inf. Comput. Sci, Vol.42, p.36-45
• M. Schröder, M. Bogdan, W. Rosenstiel, T. Hinterberger, U. Strehl, N. Birbaumer
   Online classification of EEG signals using artificial neural networks for biofeedback training of patients with epilepsy
  9th International Workshop on Systems, Signals and Image Processing, Recent trends in Multimedia Information Processing, World Scientific Press, Manchester
• A. Braun, C. Hansen, J. Gerlach, W. Rosenstiel
   Test Bench Support for SystemC Specifications
  In Proceedings of Forum on Specification & Design Languages (FDL)

Publikationen von 2001

• E. Sapozhnikova, E. Lunin, W. Rosenstiel
   A modified search procedure for the Fuzzy ARTMAP neural network
  In Proceedings of the 3d Conference "Neuroinformatics", Vol.1, p.86-92, Moscow, Russia

• T. Kuhn, T. Oppold, M. Winterholer, W. Rosenstiel, M. Edwards, , Y. Kashai
    A Framework for Object Oriented Hardware Specification, Verification, and Synthesis
  38. Design Automation Conference (DAC), Las Vegas, USA
• C. Schluz-Key, T. Kuhn, W. Rosenstiel
   A Framework for System-Level Partitioning of Object-Oriented Specifications
  Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
• E. Sapozhnikova, V. Lunin, W. Rosenstiel
   A modification of FAM
  In Proceedings of the 7th Conference "Neurocomputers and their application", p.587-590, Moscow, Russia
• E. Sapozhnikova, L. Ludwig, W. Rosenstiel
   A Modification of the Fuzzy ARTMAP Algorithm
  Proceedings of the 5th World Multi-Conference on Systemics, Cybernetics and Informatics (SCI)
• C. Hansen, O. Bringmann, W. Rosenstiel
   A VHDL Reuse Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis
  System-on-Chip Methodologies & Design Languages, edited by P.J. Ashenden, J.P. Mermet and R. Seepold (Buch);, Kluwer Academic Publishers
• C. Fietzek, T. Hermle, W. Rosenstiel, V. Schurig
   Chiral discrimination of limonene by use of ß-cyclodextrin-coated quartz-crystal-micro-balances (QCMs) and data evaluation by artificial neuronal networks
  Fresenius J Anal Chem, Nr.1, p.58-63
• M. Bogdan, W. Rosenstiel
   Detection of Cluster in Self-Organizing Maps for Controlling a Prostheses using Nerve Signals
  ESANN, Brugge
• M. Hipp, S. Kunze, M. Ritt, W. Rosenstiel, H. Ruder
   Fast parallel particle simulations on distributed memory architectures
  E. Krause and W. Jäger (editors), High Performance Computing in Science and Engineering
• A. Vörg, R. Seepold, A. H. G. Martinez, W. Rosenstiel
   IP-Qualification, Reuse, IP-Packaging
  Forum on Design Languages (FDL)
• A. Vörg, A. H. G. Martinez, R. Seepold, W. Rosenstiel
   IP-Qualifizierung wiederverwendbarer Schaltungsbeschreibungen
  Entwurf Integrierter Schaltungen, 10. E.I.S.-Workshop
• S. Schmitt, W. Rosenstiel
   Java in eingebetteten Systemen
  it + ti – Informationstechnik und Technische Informatik, Vol.43, Oldenbourg Verlag
• S. Schmitt, W. Rosenstiel
   Konzeption einer adaptiven und dynamisch konfigurierbaren Laufzeitumgebung für echtzeitkritische eingebettete Systeme
  Arbeitsplatzcomputer (APC), VDE Verlag
• E. Sapozhnikova, V. P. Lunin, W. Rosenstiel
   Modified search in Fuzzy ARTMAP
  Proceedings of the Conference "Neuroinformatics"
• T. Kuhn, T. Oppold, C. Schulz-Key, M. Winterholer, W. Rosenstiel, M. Edwards, , Y. Kashai
    Object Oriented Hardware Synthesis and Verification
  14. International Symposium on System Synthesis (ISSS), Montréal, Québec, Kanada
• S. Pinkenburg, M. Ritt, W. Rosenstiel
   Parallelization of an object-oriented particle-in-cell simulation
  Workshop Parallel Object-Oriented Scientific Computing (OOPSLA)
• M. Bogdan, M. Franke, W. Rosenstiel
   Real Time Processing of Nerve Signals for Controlling an Artificial Hand
  IASTED International Conference on Applied Informatics AI, Innsbruck
• J. Ruf, M. Hoffmann, T. Kropf, W. Rosenstiel
   Simulation-Guided Property Checking Based on Multi-Valued AR-Automata
  Proceedings of Design Automation and Test in Europe (DATE)
• W. Lange, W. Rosenstiel
   Synthesis of Data Transmission Circuits Starting from Behavioral HW Descriptions
  Proceedings of the ICECS, the 8th International Conference on Electronics, Circuits and Systems
• D. Krause, W. Jäger, M. Resch, J. Gerlach, W. Rosenstiel
   System Level Design. Using the SystemC Modeling Platform
  Merker, Schwarz (Eds.): System Design Automation, ISBN 0-7923-7313-8, Kluwer Academic Publishers
• J. Ruf, M. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiel
   The Simulation Semantics of SystemC
  Proceedings of Design Automation and Test in Europe (DATE)
• S. Schmitt, W. Rosenstiel
   Tutorial Real Time Java for Embedded Systems
  Proceedings of Design, Automation and Test in Europe (DATE)
• U. Haug, W. Rosenstiel
   VLIW-Prozessorbasierte Emulation und Prototyping digitaler Schaltungen Entwurf Integrierter Schaltungen
  10. E.I.S.-Workshop

Publikationen von 2000

• J. Gerlach, W. Rosenstiel
    A Methodology and Tool for Automated Transformational High-Level Design Space Exploration
  International Conference on Computer Design (ICCD), Austin, Texas, USA
• J. Gerlach, W. Rosenstiel
   Object-Oriented Design of System-on-Chip with SystemC - Concepts and Examples (Tutorial)
  Forum on Design Languages (FDL), Tübingen

• U. Heuser, W. Rosenstiel
   Automatic Construction of Local Internet Directories using Hierarchical Radius-based Competitive Learning
  In Proceedings of the 4th World Multiconference on Systemics, Cybernetics and Informatics (SCI), ISBN 980-07-6690-1, invited paper, Vol.4, p.436-441, Orlando, Florida

• J. Gerlach, W. Rosenstiel
    SystemC: A C++ Based Modeling Platform for System Level Design
  Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI), Kyoto, Japan

• J. Gerlach, W. Rosenstiel
    System Level Design Using the SystemC Modeling Platform
  Workshop on System Design Automation (SDA), p.185-189, Rathen

• E. Sapozhnikova, T. Hermle, L. Ludwig, V. Lunin, W. Rosenstiel
   ART Neural Networks in the Analysis of Monitoring Data
  Eighteenth IASTED International Conference on Applied Informatics (AI), Innsbruck, Austria
• E. Sapozhnikova, V. Lunin, L. Ludwig, W. Rosenstiel
   Neural prediction of chip quality on the basis of monitoring data
  In Proceedings of the 6th Conference "Neurocomputers and their application", Moscow, Russia

• U. Haug, U. Kebschull, W. Rosenstiel
   A Hardware Platform for VLIW Based Emulation of Digital Designs
  Proceedings of Design, Automation and Test in Europe (DATE)
• U. Heuser, W. Rosenstiel
   Automatic Generation of Local Internet Catalogues using Hierarchical Radius-based Competitive Learning
  W. Horn (ed.): ECAI. Proc. of the 14th European Conference on Artificial Intelligence (ECAI), p.306-310, IOS Press, Amsterdam
• J. Ruf, M. Hoffmann, T. Kropf, W. Rosenstiel
   Checking Temporal Properties under Simulation of Executable Specifications
  Proceedings of Workshop on High Level Design, Validation and Test (HLDVT)
• T. Buchholz, W. Rosenstiel
   Constraint-based Specification of Complex Components
  Hardware Description Languages Conference (HDLCON)
• E. Sapoznikova, L. Ludwig, W. Rosenstiel
   Die Anwendung des dARTMAP-Netzes zur Analyse von elektrischen Parametern in der Chip-Fertigung
  VDI-Bericht, Vol.1526
• K. Beschorner, W. Rosenstiel
   Effiziente Datenübertragung in EJB-Systemen
  Proceedings of Net. ObjectDays
• U. Haug, U. Kebschull, W. Rosenstiel
   Emulation synthetisierter Verhaltensbeschreibungen mit VLIW-Prozessoren
  GI/ITG Workshop
• L. Ludwig, E. Sapozhnikova, V. Lunin, W.Rosenstiel
   Error Classification and Yield Prediction of Chips in Semiconductor Industry Applications
  Neural Computing & Applications, Vol.9, p.202-210, Springer, London
• O. Bringmann, W. Rosenstiel
   Hierarchische Synthese für anwendungsspezifische Prototypenimplementierungen
  it + it – Informationstechnik und Technische Informatik, Vol.42, Oldenbourg Verlag
• W. Lange, W. Rosenstiel
   Modeling and Synthesis of Data Transmission Control Logic Using the Protocol CompilerTM
  Forum on Design Languages (FDL)
• E. Sapozhnikova, V. P. Lunin, L. Ludwig, W. Rosenstiel
   Neuronale Algorithmen in Qualitaetssicherung von Chips
  Zeitschrift Neurocomputer: Entwicklung und Anwendung, Vol.3
• L. Ludwig, W. Rosenstiel
   Neuronale Netze für industrielle Anwendungen
  Handouts CeBIT
• W. Rosenstiel, L. Ludwig
   Neuronale Netze in der industriellen Qualitätssicherung
  CeBit
• W. Rosenstiel, M. Bogdan
   Neuronale Netze: Nervengesteuerte künstliche Hand
  CeBit
• T. Kuhn, C. Schluz-Key, W. Rosenstiel
   Object Oriented Hardware Specification with Java
  Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
• T. Grundmann, M. Ritt, W. Rosenstiel
   Object-Oriented Message-Passing with TPO++
  In: Arndt Bode, Thomas L. Ludwig, Wolfgang Karl, and Roland Wissmüller (eds.), Euro-Par Parallel processing, Springer Verlag
• M. Schröder, M.Bogdan, W. Rosenstiel
   Restoration of Hand Function using Artificial Neural Net Controller
  IASTED International Conference on Control and Applications CA, ISBN 0-88986-288-5, Cancun
• R. Seepold, A. H. G. Martinez, M. Madrid, W. Rosenstiel
   Reuse of Virtual Components in System-on-Chip Environments
  Proceedings of Design, Automation and Test in Europe (DATE)
• M. Bogdan, W. Rosenstiel
   Self-Organized Real Time Controller for Limb Prostheses
  IASTED International Conference on Control and Applications CA, ISBN 0-88986-288-5, Cancun
• J. Ruf, M. Hoffmann, T. Kropf, W. Rosenstiel
   Simulation Based Validation of FLTL Formulas in Executable System Descriptions
  Forum on Design Languages (FDL)
• M. Hoffmann, J. Ruf, T. Kropf, W. Rosenstiel
   Simulation Meets Verification – Checking Temporal Properties in SystemC1
  Proceedings of the Symposium on Digital Systems Design (DSD)
• W. Lange, W. Rosenstiel
   Synthesis of ATM Switch Controller Modules with the Protocol CompilerTM from SynopsysTM
  WSI-00-6, Wilhelm-Schickard-Institut, Universität Tübingen
• J. Gerlach, W. Rosenstiel
   System Level Design Using the SystemC Modeling Platform
  Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI)
• J. Gerlach, W. Rosenstiel
    System Level Design Using the SystemC Modeling Platform
  R. Merker, W. Schwarz (Eds.). System Design Automation - Fundamentals, Principles, Methods, Examples. VDI Verlag Düsseldorf
• O. Bringmann, C. Menn, W. Rosenstiel
   Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
  Proceedings of Design, Automation and Test in Europe (DATE)
• T. Grundmann, M. Ritt, W. Rosenstiel
   TPO++: An Object-Oriented Message-Passing Library in C++
  In: David J. Lilja (editor), Proc. of the International Conference on Parallel Processing, IEEE Computer Society
• C. Hansen, W. Rosenstiel
   Transformation of Algorithmic Simulation Vector Sets Considering Mapping Problems of I/O Operations
  International High Level Design Validation and Test Workshop (HLDVT)
• C. Hansen, M. Pröfrock, W. Rosenstiel
   Transformation of Algorithmic Simulation Vector Sets for Automatic Reuse at RT Level
  Forum on Design Language (FDL)
• S. Schmitt, W. Rosenstiel
   Untersuchungen zur Implementierung von Java-Laufzeitumgebungen für eingebettete Systeme
  NODE

Publikationen von 1999

• J. Gerlach, W. Rosenstiel
    Ein modularer Ansatz zur Transformationssteuerung
  WSI-99-20, Wilhelm-Schickard-Institut für Informatik
• J. Gerlach, W. Rosenstiel
    Transformationale Optimierung von Entwurfsdarstellungen der algorithmischen Ebene
  WSI-99-19, Wilhelm-Schickard-Institut für Informatik

• T. Hermle, U. Weimar, W. Rosenstiel, W. Göpel
   Performance of selected Evaluation Methods for a Hybrid Sensor System
  6th Int. Symposium on Olfaction & Electronic Nose, Tübingen
• C. Fietzek, T. Hermle, S. Reich, J.Pfeiffer, M.Roeder, H.Czesla, U. Weimar, W. Rosenstiel, V. Schurig, W. Göpel
   Recognition of chiral flavoring agents using ß-cyclodextrin-coated quartz-crystal-microbalances (QCMs)
  6th Int. Symposium on Olfaction & Electronic Nose, Tübingen

• W. Rosenstiel
   Eingebettete Systeme
  Automatisierungstechnik, Theoretische Grundlagen, Methoden, Anwendungen, Vol.47, Oldenburg Verlag
• E. Hilgendorf, G. Heim, W. Rosenstiel
   Evaluation of Branch-Prediction Methods on Traces from Commercial Applications
  IBM Journal of Research and Development, Vol.43

• U. Heuser, W. Rosenstiel
   Das Hierarchische Radius-basierte Competitive Learning (HRCL) im Vergleich mit statistischen und neuronalen Clusteranalyseverfahren
  Research Report WSI 99-08, ISSN 0946-3852, Wilhelm-Schickard-Institut für Informatik, Universität Tübingen

• J. Gerlach, W. Rosenstiel
    Ein modularer Ansatz zur Automatisierung der abstrakten Entwurfsraum-Exploration.
  Workshop on System Design Automation (SDA), Rathen

• J. Gerlach, T. Klöpfer, W. Rosenstiel
    Algorithmischer Ansatz zur automatisierten Entwurfsraum-Exploration auf hoher Abstraktionsebene.
  GI/ITG/GMM Workshop on Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, p.111-120, Braunschweig

• M. Hipp, S. Hüttemann, M. Konold, M. Klingler, P. Leinen, M. Ritt, W. Rosenstiel, M. Ruder, R. Speith, H. Yserentant
   A Parallel Object-Oriented Framework for Particle Methods
  In: Krause and Jäger (edt.): High Performance Computing in Science and Engineering, Springer Verlag
• P. Maciel, W. Rosenstiel
   A Petri Net Based Approach for Estimating Area in Hardware/Software Codesign
  High Performance Computing Conference, Design Automation for Embedded Systems Journal, Kluwer Verlag
• C. Hansen, O. Bringmann, W. Rosenstiel
   A VHDL Component Model for Mixed Abstraction Level Simulation and Behavioral Synthesis
  Forum on Design Languages (FDL)
• J. Gerlach, T. Klöpfer, W. Rosenstiel
   Algorithmischer Ansatz zur automatisierten Entwurfsraum-Exploration auf hoher Abstraktionsebene
  Tagungsband Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Shaker Verlag
• C. Hansen, F. Nascimento, W. Rosenstiel
   An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications
  Proceedings of 36th Design Automation Conference (DAC)
• A. Reutter, W. Rosenstiel
   An Efficient Reuse System for Digital Circuit Design Proceedings of Design, Automation and Test in Europe
  Proceedings of Design, Automation and Test in Europe (DATE)
• C. Hansen, O. Uhlmann, W. Rosenstiel
   An Interface Description Model for Reuse of Algorithmic Hardware Specifications
  GI-Workshop Hardwarebeschreibungssprachen und Modellierungsparadigmen
• E. Sapozhnikova, Lunin, L. Ludwig, W. Rosenstiel
   Anwendung Neuronaler Netze (ART) zur Qualitätsprüfung von Wafern
  In Proceedings der Tagung: Neuro-Computer und seine Anwendung, p.153-156, Moskau, Russland
• M.Bogdan, W. Rosenstiel
   Application of Artificial Neural Networks for Different Engineering Problems
  Lecture Notes in Computer Science 1725, 26th Annual Conference on Current Trends in Theory and Practice of Informatics SOFSEM, Invited paper, Milovy
• T. Kuhn, W. Rosenstiel, U. Kebschull
   Beschreibung und Simulation von Hardware/Software-Systemen mit Java
  GI/ITG/GMM Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen
• F. Tacke, A. Cechin, L. Ludwig, M. Mack, W. Rosenstiel
   Classification of Helix and Scheet Structures in Proteins
  WSI-99, Wilhem-Schickard-Institut, Universität Tübingen
• B. Koppenhöfer, Jakob, S. Würthner, W. Rosenstiel, X. Zhu, Z. Lin
   Creating Knowledge on the Separation of Enantiomers of Drugs
  21st International Symposium on Capillary Chromatography and Electrophoresis
• W. Dreher, H. G. Martin, W. Rosenstiel
   Das Weaver-II-Board als neue HW/SW-Codesign Plattform
  SDA
• S. Schmitt, W. Rosenstiel
   Der Einsatz von Jini für die Realisierung durchgängiger Steuerungskonzepte in verteilten eingebetteten Systemen
  JIT 99
• T. Kuhn, W. Rosenstiel, U. Kebschull
   Description and Simulation of Hardware/Software Systems
  36th Design Automation Conference (DAC)
• J. Gerlach, W. Rosenstiel
   Ein modularer Ansatz zur Transformationssteuerung
  WSI 99-20, Wilhelm-Schickard-Institut, Universität Tübingen
• J. Gerlach, W. Rosenstiel
   Ein modularer Steuerungsansatz zur Automatisierung der abstrakten Entwurfsraum-Exploration
  SDA
• K. Weiß, T. Steckstor, W. Rosenstiel
   Emulation of a Fast Reactive Embedded System using a Real Time Operating System
  Proceedings of Design, Automation and Test in Europe (DATE)
• W. Rosenstiel
   Entwurfsmethoden für eingebettete Systeme
  it+ti-Informationstechnik und Technische Informatik, Vol.41, Oldenburg Verlag, München
• K. Weiß, T. Steckstor, G. Koch, W. Rosenstiel
   Exploiting FPGA-Features during the Emulation of a Fast Reactive Embedded System
  FPGA
• H. G. Martin, W. Rosenstiel
   FPGA-Design unter besonderer Berücksichtigung von Multiplexer-Struktur und Verdrahtbarkeit
  WSI-99, Wilhelm-Schickard-Institut, Universität Tübingen
• A. Kress, U. Haug, U. Kebschull, W. Rosenstiel
   Hardware/Software System Prototyping using VLIW Architectures
  In: J. -Y. Roger et. al. (eds.): Business and Work in the Information Society/New technologies and Applications, IOS Press
• O. Bringmann, W. Rosenstiel
   Hierarchische Synthese für die Emulation von integrierten Steuerungssystem
  , Wilhelm-Schickard-Institut, Universität Tübingen
• O. Bringmann, W. Rosenstiel
   Hierarchische Synthese für die Emulation von integrierten Steuerungssystemen
  Informatik '99 - 29. Jahrestagung der Gesellschaft für Informatik, Informatik aktuell, Springer Verlag
• W. Lange, W. Rosenstiel
   High-Level-Synthese einer ATM-Switch-Steuerung mit dem Behavioral CompilerTM von SynopsysTM
  WSI-99-1, Wilhelm-Schickard-Institut, Universität Tübingen
• A. Hergenhan, C. Weiler, W. Rosenstiel
   Internet-basierte eingebettete Systeme in der industriellen Automation
  At 7/99, Automatisierungstechnik 47, Theoretische Grundlagen, Methoden, Anwendungen, Oldenburg Verlag
• S. Schmitt, W. Rosenstiel
   Konzeption und Realisierung eingebetteter Systeme im Internet
  WSI-99-3, Wilhelm-Schickard-Institut, Universität Tübingen
• O. Bringmann, W. Rosenstiel, K. Muth, Färber, F. Slomka, H. Hofmann
   Mixed Abstraction Level Hardware Synthesis from SDL for Rapid Prototyping
  Proceedings of 10th Workshop on Rapid System Prototyping
• J. Wunner, W. Rosenstiel
   Multimedia in der Hochschullehre – Ein Überblick über die Grundlagen und aktuelle Konferenz-Werkzeuge
  WSI-99-07, Wilhelm-Schickard-Institut, Universität Tübingen
• U. Heuser, A. Babanine, D. Petoukhov, W. Rosenstiel,
   Neural Networks Subsystem
  A. Patel, L. Petrosjan, W. Rosenstiel (Eds.): OASIS: Distributed Search System in the Internet, ISBN 5-7997-0138-0, p.614, St. Petersburg State University Published Press, St. Petersburg
• S. Hüttemann, M. Hipp, M. Ritt, W. Rosenstiel
   Object Oriented Concepts for Parallel Smoothed Particle Hydrodynamics Simulations
  Proceedings of the Workshop on Parallel/High-Performance Object-Oriented Scientific Computing (POOSC), Interner Bericht, Forschungszentrum Jülich, Zentralinstitut für Angewandte Mathematik
• C. Barna, W. Rosenstiel
   Object Oriented Reuse Methodology for VHDL
  Proceedings of Design, Automation and Test in Europe (DATE)
• K. Weiß, T. Steckstor, W. Rosenstiel
   Performance Analysis of a RTOS by Emulation of an Embedded System
  IEEE International Workshop on Rapid System Prototyping
• W. Rosenstiel
   Rapid Prototyping, Emulation and Hardware-Software Co-Debugging
  System-Level Synthesis, Series E: Applied Sciences , Vol.357
• S. Schmitt, W. Rosenstiel
   Realisierungsmöglichkeiten eingebetteter Systeme im Internet
  GMM/GI/ITG Workshop Entwurf integrierter Schaltungen
• T. Bubeck, M. Hipp, S. Hüttemann, S. Kunze, M. Ritt, W. Rosenstiel, M. Ruder, R. Speith
   SPH test simulations on a portable parallel environment
  Proceedings of the Workshop on Physics and Computer Science, Spring meeting of the DPG
• E. Sapozhnikova, Lunin, L. Ludwig, W. Rosenstiel
   The Use of dARTMAP and FUZZY ARTMAP to solve the Quality testing Task in Semiconductor Industry
  In Proceedings of KES, p.361-364, Adelaide, Australia
• J. Gerlach, W. Rosenstiel
   Transformationale Optimierung von Entwurfsdarstellungen der algorithmischen Ebene
  WSI 99-19, Wilhelm-Schickard-Institut, Universität Tübingen
• E. Sapozhnikova, V. P. Lunin, L. Ludwig, W. Rosenstiel
   Using the Neural Networks dARTMAP and Fuzzy ARTMAP for Quality Testing Task in Semiconductor Industry
  Proceedings of ANNIE 99
• E. Sapozhnikova, Lunin, L. Ludwig, W. Rosenstiel
   Using the Neural Networks on the Basis of Adaptive Resonance Theory to Quality Testing in Semiconductor Industry
  In Proceedings of EANN, p.236-240, Warsaw, Poland
• W. Lange, W. Rosenstiel
   VHDL Description and High-Level Synthesis of an ATM Layer Circuit
  EUROMICRO
• W. Lange, W. Rosenstiel
   VHDL Design and High-Level Synthesis of an ATM Switch Controller
  Forum on Design Languages (FDL)
• U. Haug, U. Kebschull, W. Rosenstiel
   VLIW Based Emulation of Digital Designs with the RAVE System
  International High Level Design Validation and Test Workshop (HLDVT)

Publikationen von 1998

• A. Reutter, B. Mößner, W. Rosenstiel
   Design of reusable modules for high level designs
  International Workshop on IP based synthesis and system design, Grenoble
• O. Bringmann, W. Rosenstiel, S. Reichardt
   Synchronization Detection in Multi-Process Hierarchical Synthesis
  11th International Symposium on System Synthesis (ISSS), Hsinchu, Taiwan
• Steckelbach, T. Bubeck, U. Fößmeier, M. Kaufmann, M. Ritt, W. Rosenstiel
   Visualization of Parallel Execution Graphs
  Symposium on Graph Drawing, Lecture Notes in Computer Science

• J. Gerlach, W. Rosenstiel
   Development of a High-Level Design Space Exploration Methodolog
  WSI 98-13, ISSN 0946-3852, SFB 358, Universität Tübingen
• J. Gerlach, W. Rosenstiel
    Development of a High-Level Design Space Exploration Methodology
  WSI-98-13, Wilhelm-Schickard-Institut für Informatik
• K. Beschorner, W. Rosenstiel
   Realisierung einer Client/Server-Anwendung mit CORBA und Java unter Berücksichtigung bestehender C++-Komponenten
  Java-Informations-Tage (JIT), erschienen in Informatik aktuell, Springer Verlag, Frankfurt/Main
• J. Gerlach, W. Rosenstiel
    Software Modules for Format Conversion, Transformation and Synthesis
  

• F. Nascimento, W. Rosenstiel
   A co-synthesis approach based on symbolic reachability analysis
  10. Brazilian Symposium on Integrated Circuit Design, Rio de Janeiro, Brazil

• T. Hermle, U. Weimar, W. Rosenstiel, W. Göpel
   Feature Extraction for a Hybrid Gas Sensing System
  In Proceedings of 5th Int. Symposium on Olfaction & Electronic Nose, Baltimore
• F. Heuser, W. Rosenstiel
   Internetsuche und Neuronale Netze - Stand der Technik
  Research Report WSI 98-10, ISSN 0946-3852, Wilhelm-Schickard-Institut für Informatik, Universität Tübingen
• J. Gerlach, W. Rosenstiel
    Transformationale Entwurfsraum-Exploration.
  43. International Scientific Colloquium Ilmenau (IWK), Ilmenau

• W. Rosenstiel
   Rapid Prototyping, Emulation and Hardware-Software Co-Debugging
  NATO advanced Study Institute on System Level Synthesis, Il Ciocco, Italy

• F. Nascimento, W. Rosenstiel
   Co-Synthesis Using a Partial Order Based Model of Concurrency
  Workshop on Design, Test and Applications, Dubrovnik, Croatia
• H. Garcez, W. Rosenstiel
   Constraints as Temporal Logic Formulas and its Verification using Model Checking
  Workshop on Design, Test and Application, Dubrovnik, Croatia

• K. Weiß, R. Kistner, A. Kunzmann, W. Rosenstiel
   Analysis of XC6000 Architecture for Embedded System Design
  IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) , Napa, CA, USA
• U. Haug, W. Rosenstiel
   Reconfigurable Hardware as Shared Resource for Parallel Threads
  IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) , Napa, CA, USA

• A. Reutter, B. Mößner, W. Rosenstiel
   Design of generic components for efficient reuse in high level designs
  Proceedings of Workshop on System Design Automation (SDA), Dresden
• J. Gerlach, W. Rosenstiel
    Eine Umgebung zur transformationalen Entwurfsraum-Exploration.
  GI/ITG/GMM Workshop on Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, p.59-66, Paderborn
• C. Trautwein, W. Rosenstiel
   Elektronik-CAD-Anwendungen im www
  GI-Fachtagung, Tele-CAD-Produktentwicklung in Netzwerken (CAD), Darmstadt
• U. Heuser, A. Babanine, W. Rosenstiel
   HTML Documents Classification using (Non-linear) Principal Component Analysis and Self-Organizing Maps
  Proc. of the Fourth International Conference on Neural Networks and their Applications (Neurap), p.291-295, Marseilles, France
• T. Kuhn, W. Rosenstiel
   Java Based Modeling And Simulation Of Digital Systems On Register Transfer Level
  Proceedings of Workshop on System Design Automation (SDA), Dresden
• J. Gerlach, W. Rosenstiel
   Transformational Optimization of the Full Rate Speech Transcoder GSM 06.10
  Proceedings of Workshop on System Design Automation (SDA), Dresden

• H. G. Martin, W. Rosenstiel
   A Comparing Study of Technology Mapping for FPGA
  Proceedings of Design, Automation and Test in Europe (DATE), Paris
• J. Gerlach, W. Rosenstiel
   A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment
  Proceedings of Design, Automation and Test in Europe (DATE), Paris
• J. Gerlach, W. Rosenstiel.
    A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment.
  Design, Automation and Test in Europe (DATE), p.226-231, Paris, Frankreich
• O. Bringmann, W. Rosenstiel
   Cross-Level Hierarchical High-Level Synthesis
  Proceedings of Design, Automation and Test in Europe (DATE), Paris
• C. Hansen, A. Kunzmann, W. Rosenstiel
   Verification by Simulation Comparison using Interface Synthesis
  Proceedings of Design, Automation and Test in Europe (DATE), Paris

• U. Haug, T. Buchholz, U. Kebschull, G. Koch, W. Rosenstiel
   Behavioral Emulation of Synthesized RT-level Descriptions Using VLIW Architectures
  Proceedings of 9th RSP, Leuven, Belgium
• G. Koch, U. Kebschull, W. Rosenstiel
   Breakpoints and Breakpoint Detection in Source Level Emulation
  ACM Transactions on Design Automation of Electronic Systems, Vol.3(2)
• Tacke, A. Cechin, L. Ludwig, Mack, W. Rosenstiel
   Classification of Alpha-helix and Beta-sheet structures in proteines
  Proceedings of EANN, p.185-189, Gibraltar, UK
• H. Garcez, W. Rosenstiel
   Coverification Framework
  SBCCI 98 Búzios, RJ pag, p.103-107, IEEE Press
• R. Fernández, G. Koch, M. Madrid, A. B. Vallejo, W. Rosenstiel
   Hardware-Software Prototyping from LOTOS
  Design Automation for Embedded Systems 3, ISSN 0929-5585, p.117-148, Kluwer Academic Publishers
• W. Lange, W. Rosenstiel
   High-Level-Synthese einer ATM-Switch-Steuerung mit Monet
  WSI-98-14, ISSN 0946-3852, Universität Tübingen, Wilhelm-Schickard-Institut,
• L. Ludwig, W. Rosenstiel
   Neuronale Netze in Industrie und Forschung
  Handouts CeBIT
• T. Kuhn, W. Rosenstiel, U. Kebschull
   Object Oriented Hardware Modeling and Simulation Based on Java
  International Workshop on IP Based Synthesis and System Design , Grenoble
• T. Bubeck, M. Hipp, S. Hüttemann, S. Kunze, M. Ritt, W. Rosenstiel, M. Ruder, R. Speith
   Parallel SPH on CRAY T3E and NEC SX-4 using DTS
  In: E. Krause, W. Jäger (Eds.): High Performance Computing in Science and Engineering, Transactions of the High Performance Computing Center Stuttgart (HLRS), Springer-Verlag
• H. Garcez, F. Nascimento, W. Rosenstiel
   POM Semantics for 1-safe Petri Nets
  WOLLIC, Sao Paulo, Brasilien
• L. Ludwig, Pelz, Kessler, Sinderhauf, Koppenhoefer, W. Rosenstiel
   Prediction of functional yield of chips in semiconductor industry applications
  In Proceedings of EANN, p.157-161, Gibraltar, UK
• M. Bogdan, W. Rosenstiel
   Real Time Processing of Nerve Signals for Controlling a Limb Prostheses
  In Information Processing in Cells and Tissues, Edited by Mike Holcombe and Ray Paton, ISBN 0-306-45839-X, p.17-25
• U. Haug, W. Rosenstiel
   Reconfigurable Hardware as Shared Resource in Multipurpose Computers in Field-Programmable Logic Applications
  LNCS 1482, Springer Verlag, Heidelberg
• J. Gerlach, W. Rosenstiel
    Transformational Optimization of the Full Rate Speech TranscoderGSM 06.10.
  Open Project Workshop on System Design Automation (SDA), p.68-73, Dresden
• A. Hergenhan, C. Weiler, K. Weiß, W. Rosenstiel
   Value-Added Services in Industrial Automation Proceedings of International Workshop on Advanced Communication Services
  , Lisbon

Publikationen von 1997

• W. Rosenstiel
   Eingebettete Systeme im Internet - Technologie für die weltweite Automation
  Handzettel zu INTERTECH BODENSEE, Friedrichshafen
• W. Rosenstiel
   Eingebettete Systeme im Internet - Technologie für die weltweite Automation
  Handzettel zu INTERTECH BODENSEE, Friedrichshafen
• W. Rosenstiel
   Embedded Systems on a Chip
  11th German-Japanese Forum on Information Technology, Nagano, Japan
• W. Rosenstiel, M. Bogdan
   Neuronale Netze: Nervengesteuerte Prothese
  Exponat Handout Medica, Düsseldorf
• O. Bringmann, W. Rosenstiel
   Resource Sharing in Hierarchical Synthesis
  ICCAD, San José, CA, USA

• U. Heuser, J. Göppert, W. Rosenstiel, A. Stevens
   Classification of Human Brain Waves using Self-Organizing Maps
  In Intelligent Data Analysis in Medicine and Pharmacology, edited by N. Lavrac, E. Keravnou, B. Zupan, The Kluwer International Series in Engineering and Computer Science, ISBN 0-7923-8000-2, Vol.414, p.279-294, Kluwer Academic Publishers, Boston, USA
• G. Koch, U. Kebschull, W. Rosenstiel
   Co-Emulation and Debugging of HW/SW-Systems
  10th Intern. Symposium on System Synthesis (ISSS), Antwerpen
• H. Garcez, W. Rosenstiel
   Coverification of timing properties
  International Workshop on Conjoint Systems Engineering CONSYSE, Bad Tölz
• S. Reich, F. J. Rammig, W. Rosenstiel, D. Schmid, K. Waldschmidt
   DFG-Schwerpunktprogramm: „Entwurf und Entwurfsmethodik eingebetteter Systeme“
  informatik aktuell, 27. Jahrestagung der Gesellschaft für Informatik, Springer Verlag, Aachen
• J. Gerlach, W. Rosenstiel
   Ein skalierbarer Ansatz zur Kostenabschätzung für die Steuerung von High-Level Transformationen
  WSI 97-5, SFB 358, Universität Tübingen
• F. Nascimento, W. Rosenstiel
   Partial order based modeling of concurrency at the system level
  International Workshop on Conjoint Systems Engineering (CONSYSE), Bad Tölz
• K. Weiß, A. Hergenhan, W. Rosenstiel
   Systematischer Entwurf und Test eingebetteter Systeme am Beispiel eines ATM-Diagnosesystems
  GI/ITG-Workshop Zielarchitekturen Eingebetteter Systeme, Roststock

• P. Maciel, E. Barros, W. Rosenstiel
   Using Petri Nets to Compute Communication Costs for Hardware/Software Codesign
  10. Brazilian Symposium on Integrated Circuit Design (SBCCI), Gramado, RS, Brazil

• L. Ludwig, U. Epperlein, H. H. Kuge, P. Federl, B. Koppenhöfer, W. Rosenstiel
   Classification of ‘Fingerprints’ of Process Control Monitoring-Data with Self-organizing Maps
  Proceedings of EANN, Stockholm
• P. Maciel, E. Barros, W. Rosenstiel
   Computing Communication Cost by Petri Nets for Hardware/Software Codesign
  Rapid System Prototyping Proceedings, Capel Hill, North Carolina, USA
• J. Gerlach, W. Rosenstiel.
    Ein skalierbarer Ansatz zur Kostenabschätzung für die Steuerung von High-Level Transformationen.
  GI/ITG/GMM Fachgruppentreffen 3. 5. 7/5. 2. 2/5. 7, Technical Report WSI-97-5, Wilhelm-Schickard-Institut für Informatik, Universtität Tübingen
• C. Weiler, A. Kunzmann, W. Rosenstiel
   Performance Analysis for a Java-based Virtual Prototype
  International Workshop on Rapid System Prototyping, Chapel Hill, USA
• J. Göppert, W. Rosenstiel
   The Continuous Interpolation Self-organizing Map
  Neural Processing Letters Volume, Vol.5(3), Kluwer Academic Publishers

• W. Hardt, W. Rosenstiel
   Prototyping of Tightly Coupled Hardware/Software-Systems
  Design Automation for Embedded Systems, Vol.2(3-4), p.283-317, Kluwer Academic Press

• J. Wilberg, A. Kuth, W. Rosenstiel, H. T. Vierhaus
   A Design Management System for the WWW
  8. E.I.S. -Workshop, Universität Hamburg
• R. Seepold, A. Kunzmann, W. Rosenstiel
   Eine effiziente objekt-orientierte Wiederverwendungsmethode für den Hardware-Entwurf
  8. E.I.S. -Workshop, Universität Hamburg
• T. Buchholz, U. Kebschull, W. Rosenstiel
   Emulation komplexer synthetisierter Schaltungen auf Signalprozessoren
  8. E.I.S. -Workshop, Universität Hamburg
• X. Fang, P. Thole, W. Rosenstiel
   Hardware-Software Co-Entwurf für Kohonen’s SOM
  8. E.I.S. -Workshop, Universität Hamburg
• M. Theißinger, H. T. Vierhaus, W. Rosenstiel
   Kombinierte Registerzuordnung und Instruktionsablaufplanung für irreguläre Architekturen
  8. E.I.S. -Workshop, Universität Hamburg
• P. Thole, W. Rosenstiel
   Speicherallokation vor der High Level Synthese mit Profilinginformationen
  8. E.I.S. -Workshop, Universität Hamburg
• A. Reutter, B. Mößner, Kreuzer, W. Rosenstiel
   Wiederverwendung komplexer Komponenten für Synthese und Simulation unter Verwendung von VHDL
  8. E.I.S. -Workshop, Hamburg

• W. Rosenstiel, M. Bogdan
   Neuronale Netze: Nervengesteuerte Prothese
  Handout CEBIT, Hannover
• W. Rosenstiel, A. Cechin
   Neuronale Netze: Wissensextraktion aus Neuronalen Netzen
  Handout CEBIT, Hannover
• W. Rosenstiel, A. Babanine
   Wiederherstellung von Farben mit Neuronalen Netzen
  Handout CEBIT, Hannover

• C. Hansen, P. Gutberlet, A. Kunzmann, W. Rosenstiel
   Automatischer Taktzyklenabgleich zur Simulation in der High-Level Synthese
  Workshop Hardwarebeschreibungssprachen und Modellierungsparadigmen, Holzau

• B. Koppenhöfer, S. Würthner, L. Ludwig, W. Rosenstiel
   Analysis of Electrical Test Data Using a Neural Network Approach
  Kongressbeitrag IEEE/SEMI ASMC, Cambridge, USA
• A. Babanine, A. Cechin, H. Resch, W. Rosenstiel
   Artificial Neural Networks for the Restoration of Colours in Scanned Images
  In proceedings to IMACS, Vol.4, p.441-336, Berlin
• L. Ludwig, Epperlein, Kuge, Federl, Koppenhöfer, W. Rosenstiel
   Classification of 'Fingerprints' of Process Control Monitoring-Data with Self-organizing Maps
  In Proceedings of EANN, p.107-111, Stockholm, Sweden
• M. Bogdan, A. Cechin, S. Breit, W. Rosenstiel
   Cultured Nerve Cell Networks as Biosensors using Artificial Neural Nets
  Seizième Colloque sur le Traitement du Signal et des Images GRETSI'97, Grenoble
• J. Gerlach, W. Rosenstiel.
    Ein hierarchischer Evaluierungsansatz zur Steuerung von High-Level Transformationen
  SFB 358-B3-2/97, TU Dresden
• M. Bogdan, A. Harsch, G. Gross, W. Göpel, W. Rosenstiel
   Processing of Nerve Cell Signal Recordings from Cultured Neural Networks using Artificial Neural Nets
  Conf. IASTED Intelligence and Soft Computing, Banff
• W. Rosenstiel
   Prototyping and Emulation Hardware/Software Co-Design
  , p.75–112, Kluwer Academic Publishers
• M. Bogdan, W. Rosenstiel
   Real Time Processing of Nerve Signals for Controlling a Limb Prostheses
  Conf. Information Processing in Cells and Tissues, Sheffield
• J. Gerlach, W. Rosenstiel.
    Transformationale Optimierung des Vollraten-Sprachtranscodierers GSM 06.10.
  SFB 358-B3-5/97, TU Dresden
• W. Rosenstiel, C. Weiler
   Using Java in Embedded Systems Design
  Proceedings of SASIMI, JAPAN-Osaka
• J. Gerlach, W. Rosenstiel.
    Verfahren zur Kostenabschätzung bei der Synthese digitaler Schaltungen: Stand der Technik
  SFB 358-B3-4/97, TU Dresden

Publikationen von 1996

• O. Bringmann, J. Engelhart, S. Kumar, B. Mößner, W. Rosenstiel
   Design of an Interrupt Controller with AC-8 Tools at Different Levels of Abstraction
  International Workshop on Logic and Architecture Synthesis, Grenoble, Frankreich
• R. Seepold, A. Kunzmann, W. Rosenstiel
   Hardware Design Methodology for Efficient Reuse
  2nd World Conference on Integrated Design and Process Technology, p.423-430, Austin, Texas, USA
• R. Seepold, A. Kunzmann, W. Rosenstiel
   Hardware Design Methodology for Efficient Reuse
  2nd World Conference on Integrated Design and Process Technology, p.423-430, Austin, Texas, USA

• G. Koch, U. Kebschull, W. Rosenstiel
   Breakpoints and Breakpoint Detection in Source Level Emulation
  Tagung ISSS, La Jolla, USA

• T. Bubeck, J. Schreiner, W. Rosenstiel
   Timing multi-threaded Message-Passing Programs
  In: C. A. Héritier (hrsg.): SIPAR, SIPAR-Workshop, Geneva, Schweiz

• R. Schlunk, B. Koppenhöfer, A. Cechin, W. Rosenstiel, U. Epperlein
   Are there any rules in Chiral Separation? IV: Unprecedented Prediction of GC Data by Neural Networks.
  21st International Symposium on Chromatography, Stuttgart
• H. J. Eikerling, W. Rosenstiel
   Automatic Structuring and Optimization of Hierarchical Designs
  EURO-DAC, Technical Report SFB-358-B3, Geneva, Schweiz und TU Dresden
• Bullmann, U. Kebschull, W. Rosenstiel, E. Schubert
   Library Based Technology Mapping Using Multiple Domain Representations
  EURO-DAC, Geneva, Schweiz
• B. Koppenhoefer, U. Epperlein, R. Schlunk, L. Ludwig, A. Cechin, W. Rosenstiel
   Retrieval, Classification and Prediction of Enantiomer Separation by Neural Networks
  EUROANALYSIS IX, Bologna, Italien
• W. Hardt, J. Gerlach, H. J. Eikerling, W. Rosenstiel, B. Gregory
   Using the HDL-Advisor for Shortening the System Design Loop
  Proceedings of SNUG, Technical Report SFB358-B3-6, Geneva, Schweiz und TU Dresden

• U. Heuser, J. Göppert, W. Rosenstiel, A. Stevens
   Classification of Human Brain Waves using Self-Organizing Maps
  IDAMAP-96 Workshop notes at the 12th European Conference on Artificial Intelligence (ECAI), p.37-42, Budapest, Hungary

• Crämer, J. Göppert, W. Rosenstiel
   Modeling Psychological Stereotypes in Self-Organizing Maps
  In: Malsburg et al. (eds): Artificial neural networks (ICANN), Lecture Notes in Computers Science, Vol.1112, p.905-910, Springer Verlag, Bochum

• X. Fang, P. Thole, J. Göppert, W. Rosenstiel
   A Hardware Supported System for a Special Online Application of Self-organizing Map
  IEEE International Conference on Neural Networks (ICNN), Washington DC, USA
• X. Xiong, P. Gutberlet, W. Rosenstiel
   Automatic Generation of Interprocess Communication in the PARAGON System
  7th IEEE International Workshop on Rapid System Prototyping, Porto Caras, Thessaloniki, Griechenland
• A. Cechin, U. Epperlein, W. Rosenstiel, B. Koppenhöfer
   Fuzzy Rules Extraction from Neural Networks Applied to Molecular Recognition
  International Conference on Engineering Applications of Neural Networks (EANN), London, UK
• J. Gerlach, W. Rosenstiel.
   PMOSS: Eine integrative Umgebung zum HW/SW-Entwurf.
  GI/ITG/GMM Fachgruppentreffen 3. 5. 7/5. 2. 2/5. 7, Paderborn

• W. Lange, P. Thole, W. Rosenstiel
   Modellierung einer ATM-Switch-Steuerung mit anwendungsspezifischen Funktionen
  GI/ITG-Workshop Custom Computing, ed. D. Monjau, p.73-81, Schloß Dagstuhl, Wadern

• B. Koppenhoefer, U. Epperlein, B. Christian, J. Göppert, W. Rosenstiel
   Classification of Enantiomer Separation by Neural Networks
  Analytica, München
• W. Rosenstiel, M. Bogdan
   Neuronale Netze: Nervengesteuerte Prothese
  Hannover Messe, Hannover
• B. Koppenhoefer, U. Epperlein, R. Schlunk, A. Cechin, W. Rosenstiel
   Prediction of GC Enantiomer Separation by Neural Networks
  Analytica, München
• A. Babanine, W. Rosenstiel
   Restoration of Colours in Scanned Images using Artificial Neural Networks
  27. Conference on the Control of Dynamic Systems, St. Petersburg, Russland
• A. Cechin, U. Epperlein, W. Rosenstiel, B. Koppenhöfer
   The Extraction of Sugeno Fuzzy Rules from Neural Networks
  ESANN, Bruges, Belgien
• A. Cechin, U. Epperlein, W. Rosenstiel, B. Koppenhöfer
   The Extraction of Sugeno Fuzzy Rules from Neural Networks
  Proceedings of the Workshop Rule Extraction From Trained Artificial Neural Networks Workshop, Brighton, UK
• A. Cechin, U. Epperlein, W. Rosenstiel, B. Koppenhöfer
   The Extraction of Sugeno Fuzzy Rules from Neural Networks
  In Andrews, R, Diederich, J. (eds.): Rules and Networks, p.49-54, Queensland University of Technology, Queensland, Australia
• A. Cechin, U. Epperlein, W. Rosenstiel, B. Koppenhöfer
   The Extraction of Sugeno Fuzzy Rules from Neural Networks
  In: Bulsari, Kallio, Tsaptsinos (eds.): Solving Engineering Problems with Neural Networks, p.107-110, Finnland

• H. J. Eikerling, W. Hardt, J. Gerlach, W. Rosenstiel
   A Methodology for Rapid Analysis and Optimization of Embedded Systems
  International IEEE Symposium and Workshop on ECBS, p.252-259, Friedrichshafen
• J. Gerlach, H. Eikerling, W. Hardt, W. Rosenstiel.
    Von C nach Hardware: ein integratives Entwurfskonzept.
  GI/ITG/GMM Workshop Allgemeine Methodik von Entwurfsprozessen, Paderborn

• J. Gerlach, H. Eikerling, W. Hardt, W. Rosenstiel.
    Ein Transformations-basiertes Werkzeug fuer die schnelle Analyse und Optimierung eingebetteter Systeme.
  GI/ITG/GME-Workshop Hardwarebeschreibungssprachen und Modellierungsparadigmen, Darmstadt

• J. Wilberg, A. Kuth, R. Camposano, W. Rosenstiel, H. T. Vierhaus
   A Design Exploration Environment
  GLS-VLSI
• T. Grundmann, T. Bubeck, W. Rosenstiel
   Automatisches Generieren von DTS-Kopierfunktionen für C
  Interner Bericht, WSI-96-22, ISSN 0946-3852, Technical Report 48, SFB 382, Wilhelm-Schickard-Institut, Universität Tübingen
• M. Bogdan, H. Speckmann, W. Rosenstiel
   Chips and Computers for Artificial Neural Nets
  In Sensors Update, VCH, ISBN 3-527-2-5, 1996
• M. Bogdan, W. Rosenstiel
   Classification of Nerve Signals using Kohonen`s Self-Organizing Map
  1st International Conference on Bioelectromagnetism, Tampere, Finnland
• A. Gebhart, T. Eppler, W. Rosenstiel
   Erweiterte Methoden zur automatischen Gesichtserkennung
  Interner Bericht, WSI-96-20, ISSN 0946-3852, Universität Tübingen, Wilhelm-Schickard-Institut
• M. Bogdan, W. Rosenstiel
   Intelligent Neural Interface - Signalprocessing of Nerve Signals using Artificial Neural Nets
  BioNet, GFaI, ISBN 3-00-001107-2, Invited paper, Berlin
• M. Bogdan, A. Babanine, J. Kaniecki, W. Rosenstiel
   Nerve Signal Processing using Artificial Neural Nets
  In Computation in Cellular and Molecular Biological Systems, World Scientific, ISBN 981-02-2878-3
• W. Hardt, W. Rosenstiel
   Prototyping of Tightly Coupled Hardware/Software-Systems
  In Design Automation for Embedded Systems, Technical Report SFB358-B3-4, TU Dresden
• C. Hansen, A. Kunzmann, W. Rosenstiel
   Re-use of Test Vectors for High Level Verification
  High Level Design Validation and Test Workshop, Oakland, CA, USA
• C. Trautwein, W. Rosenstiel
   Regelung der Granularität paralleler verteilter Algorithmen in MMB-Mitteilungen,
  Messung, Modellierung und Bewertung von Rechensystemen, Nr.29, p.16-20
• J. Göppert, W. Rosenstiel
   Regularized SOM-Training: A Solution to the Topology-Approximation Dilemma?
  Proceedings of Int. Conf. on Neural Networks (ICNN), Vol.1, p.38-43, IEEE Service Center, Piscataway, NJ, USA
• W. Hardt, W. Rosenstiel
   Speed-up Estimation for HW/SW-Systems
  CODES/CASHE, Pittsburgh, PA, USA
• S. Hüttemann, T. Bubeck, W. Rosenstiel
   SPH on NEC SX4/32 using DTS
  SIPAR Workshop, p.19-22, Geneva, Schweiz
• J. Göppert, W. Rosenstiel
   Varying Cooperation in SOM for Improved Function Approximation
  IEEE International Conference on Neural Networks (ICNN), Vol.1, p.1-6, IEEE Service Center, Piscataway, NJ, USA

Publikationen von 1995

• H. J. Eikerling, M. Schmidt, W. Rosenstiel
   A Fully Symbolic Framework For Area-minimizing Hardware Resynthesis
  7. IFIP TC 10, WG 10. 5 Workshop on Logic and Architecture Synthesis, Grenoble, Frankreich
• R. Seepold, A. Kunzmann, W. Rosenstiel
   A Unified Approach for Hardware/Software-Reuse
  International Workshop on Logic and Architectural Synthesis, p.283-288, Grenoble, Frankreich

• X. Fang, P. Thole, J. Göppert, W. Rosenstiel
   A Hardware Supported System for a Special Online Application of Self-organizing Map
  Chemnitzer Kolloquium, International Conference On Neural Networks (ICNN), Vol.2, p.956-961, IEEE Service Center, Piscataway, NJ, USA
• H. J. Eikerling, M. Schmidt, W. Rosenstiel
   Anwendung symbolischer Techniken zur flächenminimierenden HW-Resynthese
  7. E.I.S. Workshop, Technical Report SFB35-B3-1, Chemnitz, Germany
• E. Schubert, W. Rosenstiel
   Fläche-Zeit-Modellierung von Register-Transfer-Komponenten für die High-Level-Synthese
  7. E.I.S.-Workshop

• J. Göppert, W. Rosenstiel
   Interpolation in SOM:Improved Generalization by Iterative Methods.
  Proceedings of ICANN, p.425-434, Paris, Frankreich

• G. Koch, U. Kebschull, W. Rosenstiel
   Debugging Behavioral VHDL Specifications by Source Level Emulation
  Eurodac, Brighton, UK
• U. Weinmann, O. Bringmann, W. Rosenstiel
   Device Selection for System Partitioning
  Eurodac, Brighton, GB
• T. Bubeck, W. Rosenstiel
   Functional Parallelism on Workstation Clusters
  SFB 382, Nr.25, Universität Tübingen
• J. Schubert, A. Kunzmann, W. Rosenstiel
   Reduced Design Time by Load Distribution with CAD Framework Methodology Information
  Eurodac, Brighton, UK

• R. Seepold, A. Kunzmann, W. Rosenstiel
   Comprehensive Reuse Techniques in CAD
  11th ISPE/IEE/IFAC International Conference on CAD/CAM, Robotics and Factories of the Future CARS and FOF, Vol.1, p.376-381, Pereira, Kolumbien

• T. Kuhn, U. Kebschull, P. Thole, E. Schubert, W. Rosenstiel
   Bibliotheksorientierte Technologieabbildung synthetisierter Datenpfade
  2. GI/ITG Workshop Anwenderprogrammierbare Schaltungen, Karlsruhe
• J. Göppert, W. Rosenstiel
   Neurons with Continuous Varying Activation in Self-Organizing Maps
  International Workshop on Artificial Neural Networks, Mira and F. Sandoval (eds), From Natural to Artificial Neural Computation, Lecture Notes in Computer Science, Vol.930, p.416-426, Springer Verlag, E-Malaga-Torremolinos, Spain
• T. Bubeck, W. Rosenstiel
   Parallelisierung auf Workstations-Clustern mit dem Distributed Threads System (DTS)
  In Mackens, Rump (eds): Proc. of Software Engineering in Scientic Computing, Hamburg
• G. Koch, U. Kebschull, W. Rosenstiel
   System Validation by Source Level Emulation of Behavioral VHDL Specifications
  6th IEEE International Workshop on Rapid System Prototyping, Chapel Hill, USA

• B. Koppenhöfer, U. Epperlein, B. Christian, J. Göppert, W. Rosenstiel
   Classification of Molecular Recognition by a Kohonen Feature Map
  Cell Adhesion 3D-databases in Drug Design, Antibodies in Drug Design, International Symposium on Capillary Chromatography and Electrophoresis, Wintergreen, VA, USA
• T. Bubeck, Küchlin, W. Rosenstiel
   Symmetric Distributed Computing with Dynamic Load Balancing and Fault Tolerance
  3rd Workshop on Languages, Compilers and Run-Time Systems for Scalable Computers, Troy, New York, USA

• J. Göppert, W. Rosenstiel
   Topological Interpolation in SOM by Affine Transformations
  ESANN, Bruxelles, Belgien

• T. Kuhn, U. Kebschull, P. Thole, E. Schubert, W. Rosenstiel
   Bibliotheksorientierte Technologieabbildung synthetisierter Datenpfade
  FZI-Publikation , Karlsruhe
• C. Hansen, Ditzinger, W. Rosenstiel
   Schaltungs-Synthese mit VHDL - Erfassung der Entwurfsprobleme durch richtige Auswahl der Subsets
  CADS, SMT

• E. Barros, W. Rosenstiel
   A Clustering Approach to Support Hardware/Software Partitioning
  In: Jerzy Rosenblit and Klaus Buchenrieder: Codesign - Computer - Aided Software/Hardware Engineering , p.230-262, IEEE Press
• Schweizer-Berberich, J. Göppert, Hierlemann, Mitrovics, U. Weimar, W. Rosenstiel, W. Göpel
   Applications of Neural Network Systems to the Dynamic Response of Polymer-Based Sensor Arrays
  Sensors and Actuators, Vol.26-27, p.232-236
• W. Hardt, R. Merker, M. Kortke, D. Fimmel, C. Trautwein, J. Wedeck, W. Rosenstiel
   Automatisierter Entwurf von Varianten eines HW/SW - Systems
  Technical Report SFB358-AB-1 , Universität Paderborn, Technische Universität Dresden, Universität Tübingen
• C. Weiler, U. Kebschull, W. Rosenstiel
   C++ Base Classes for Specification, Simulation and Partitioning of a Hardware/Software System
  VLSI, Japan
• J. Wilberg, A. Kuth, R. Camposano, W. Rosenstiel, H. T. Vierhaus
   Design Exploration in CASTLE
  In: deMicheli, Otten, H. T. Vierhaus: Workshop on High Level Synthesis Algorithms Tools and Design (HILES), GMD-Studien, Vol.276, Stanford University, CA, USA
• H. J. Brand, J. Müller, W. Rosenstiel
   Eine Bewertungsmethodik für arithmetische Operatoren
  GME-Fachtagung Mikroelektronik, Baden-Baden
• J. Göppert, W. Rosenstiel
   Interpolierte Selbstorganisierende Karte in der Funktionsapproximation
  In: Bocklisch, S. F. (Hrsg.): Technologien und Neuronale Netze in der Praxis, ISBN 3-8265-1481-5, p.77-86, Shaker Verlag, Aachen
• M. Bogdan, A. Babanine, J. Kaniecki, W. Rosenstiel
   Nerve Signal Processing using Artificial Neural Nets
  Conf. Information Processing in Cells and Tissues, Liverpool
• M. Bogdan, A. Babanine, J. Kaniecki, W. Rosenstiel
   Nerve Signal Processing using Artificial Neural Nets
  Conf. Information Processing in Cells and Tissues, Liverpool
• L. Ludwig, Kessler, J. Göppert, W. Rosenstiel
   SOM with Topological Interpolation for the Prediction of Interference Spectra
  In Proceedings of EANN, p.379-389, Helsinki, Finland

Publikationen von 1994

• H. Speckmann, G. Raddatz, W. Rosenstiel
   Relations Between Generalized Fractal Dimensions and Kohonen³s Self-Organizing Map
  Neural Networks and their Applications, Marseilles, Frankreich
• J. Göppert, W. Rosenstiel
   Selective Attention and Self-Organizing Maps
  Neural Networks and their Applications, Marseille Frankreich
• A. Cechin, J. Göppert, W. Rosenstiel
   The use of Neural Networks to estimate Gas Concentrations
  Neural Networks and Their Applications, Marseille, Frankreich

• U. Kraus, J. Göppert, W. Rosenstiel, G. Gauglitz
   Neuronale Netze in der chemischen Analytik
  GIT Fachz. Lab

• M. Wendling, W. Rosenstiel, Mauer
   A Hardware Environment for Prototyping and Partitioning Based on Multiple FPGAs
  EURO-DAC, Grenoble, Frankreich
• E. Schubert, P. Thole, W. Rosenstiel
   Exercises with the Votan High-Level Synthesis System
  EUROCHIP Course on High-Level Digital System Design , IMEC, Leuven, Belgium
• P. Gutberlet, W. Rosenstiel
   Timing Preserving Interface Transformations for the Synthesis of Behavioural VHDL
  EURO-DAC, Grenoble, Frankreich

• J. Wedeck, W. Rosenstiel
   Compiling C Programs into Threads
  International Conference Massively Parallel Processing Applications and Development, Delft, Niederlande

• W. Rosenstiel, J. Göppert
   Neuronale Netze: Anwendung in der Reflexionspektroskopie
  CeBIT, Hannover

• E. Schubert, U. Kebschull, W. Rosenstiel
   Functional Decision Diagrams for Technology Mapping to Lookup-Table FPGA
  2nd Int. Workshop on FPGA, Berkeley, CA, USA

• X. Xiong, E. Barros, W. Rosenstiel
   A Method for Partitioning UNITY Language in Hardware and Software
  EURO-DAC, Grenoble, Frankreich
• G. Koch, U. Kebschull, W. Rosenstiel
   A Prototyping Environment for Hardware/Software Codesign in the COBRA Project
  CODES/CASHE, Grenoble, Frankreich
• M. Bogdan, W. Rosenstiel
   Artificial Neural Nets for Peripheral Nervous System - remoted Limb Prostheses
  Neural Networks and their Applications, Marseille
• H. Speckmann, G. Raddatz, W. Rosenstiel
   Considerations of Geometrical and Fractal Dimension of SOM to get Better Learning Results
  ICANN, Sorrento, Italien
• H. Speckmann, P. Thole, M. Bogdan, W. Rosenstiel
   Coprocessors for special neural networks: KOKOS and KOBOLD
  ICNN, p.1959-1962, Orlando, USA
• J. Wilberg, W. Rosenstiel, e. al.
   Design Flow for Hardware/Software Cosynthesis of a Video Compression System
  CODES, CASHE, Grenoble, Frankreich
• J. Göppert, W. Rosenstiel
   Dynamic Extensions of Self-Organizing Maps
  ICANN, Sorrento, Italien
• U. Weinmann, W. Rosenstiel
   Ein Partitionierungsystem für FPGA-Prototypenrealisierungen
  FPGA-Workshop, Karlsruhe
• T. Bubeck, W. Rosenstiel
   Eine Systemumgebung zum verteilten funktionalen Rechnen
  
• P. Thole, W. Rosenstiel
   Exercises on High Level Design Automation
  5th Eurochip Workshop on VLSI Design Training, Dresden
• U. Kebschull, W. Rosenstiel
   Graph-Based Representations of Boolean Canonical Forms
  GI/ITG-Workshop, Frankfurt
• H. Speckmann, G. Raddatz, W. Rosenstiel
   Improvement of learning results of the selforganizing map by calculating fractal dimensions
  ESANN, Brüssel, Belgien
• P. Gutberlet, W. Rosenstiel
   Interface Specification and Synthesis for VHDL Processes
  7th International Symp. on High-Level Synthesis, IEEE, Niagara-on-the-Lake, ON, Canada
• M. Bogdan, H. Speckmann, W.Rosenstiel
   KOBOLD - a neural coprocessor for backpropagation with online learning
  ICANN, Sorrento
• U. Weinmann, W. Rosenstiel
   Logic Module Independent Mapping for Table-Lookup FPGAs
  ACM/SIGDA Workshop on FPGAs, Berkeley, CA, USA
• U. Weinmann, W. Rosenstiel
   Network Flow base Clustering and Partitioning for FPGAs
  IFIP-Workshop on Logic and Archt. Synth, Grenoble, Frankreich
• M. L. Kessler, J. Göppert, W. Rosenstiel
   Prediction of Oxide Layer Thickness by a Topology Preserving Interpolation Method in a self-organizing Map
  In: Advances in AI - Theory and Application, Vol.2, p.99 - 104, Ontario, Kanada
• H. J. Brand, J. Müller, W. Rosenstiel
   Specification and Synthesis of Complex Arithmetic Operators for FPGAs
  4th International Workshop on Field Programmable Logic and Applications, Prag, Tschechische Republik
• E. Schubert, W. Rosenstiel
   Synthese von Register-Transfer-Elementen mit VHDL für die High-Level-Synthese
  SMT/ASIC, Nürnberg
• L. Ludwig, J. Göppert, W. Rosenstiel
   Topological Interpolation for the Training of Self-Organizing Maps
  In Proceedings of Fuzzy-Tage, Springer, Dortmund
• J. Göppert, W. Rosenstiel
   Use of neural networks in on-line analysis
  Fresenius Journal of Analytical Chemistry, Vol.349, p.367-371, Springer Verlag
• T. Bubeck, W. Rosenstiel
   Verteiltes Rechnen mit DTS (Distributed Thread System)
  SIPAR Workshop, Fribourg, Schweiz

Publikationen von 1993

• W. Rosenstiel
   Experiences with High-Level Synthesis from VHDL-Specifications
  Proceedings of Workshop on Design Methodologies for Microelectronics and Signal Processing, Gliwice, Polen
• E. Barros, W. Rosenstiel, X. Xiong
   Hardware/Software Partitioning with UNITY
  International Workshop on Hardware-Software Co-Design, Cambridge, Massachusetts, USA
• J. Göppert, W. Rosenstiel
   Self-organizing Maps vs. Backpropagation: An Experimental Study
  Workshop Design Methodologies for Microelectronics and Signal Processing, Gliwice, Polen
• J. Göppert, W. Rosenstiel
   Topology-Preserving Interpolation in Selforganizing Maps
  Neuro, Nimes, France

• J. Wedeck, W. Rosenstiel
   Codegenerierung für parallele Rechensysteme
  37. Internationales Wissenschaftliches Kolloquium, Ilmenau

• P. Thole, H. Speckmann, W. Rosenstiel
   A Hardware Supported System for Kohonen's Selforganizing Map
  3rd Int. Conference on Microelectronics for Neural Networks, International Conference on Artificial Neural Networks, Edinburgh, UK and Amsterdam, Niederlande

• H. Speckmann, W. Rosenstiel
   Ein Hardwarebeschleuniger für neuronale Netzanwendungen
  Cebit, Hannover

• E. Barros, W. Rosenstiel
   A Clustering Approach to Support Hardware/Software Partitioning
  Computer Aided Software/Hardware Engineering, IEEE Press
• C. Hansen, E. Barros, W. Rosenstiel
   A Comparison of some Specification Mechanisms to support Hardware/Software Codesign
  Second IFIP International Workshop on Hardware/Software Codesign Codes (CASHE), Innsbruck, Österreich
• H. Speckmann, P. Thole, W. Rosenstiel
   A Coprocessor for Kohonen's Selforganizing Map (COKOS)
  IJCNN, Nagoya, Japan
• H. J. Brand, J. Müller, W. Rosenstiel
   An Efficient Data Path Synthesis Strategy
  SASIMI-Workshop
• H. J. Brand, J. Müller, W. Rosenstiel
   Design of High Throughput Data Path Components
  4th ACM Phys. Design Workshop
• U. Kebschull, W. Rosenstiel
   Efficient Graph-Based Computation and Manipulation of Functional Decision Diagrams
  EDAC/Euroasic, Paris
• H. J. Brand, J. Müller, W. Rosenstiel
   Effizienter Entwurf leistungsfähiger Datenpfadkomponenten mit LORTGEN
  E.I.S.-Workshop, Tübingen
• J. Göppert, H. Speckmann, W. Rosenstiel
   Evaluation of Interference Spectra with Kohonen's Self-Organizing Map
  International Workshop on Mechatronica Computer Systems for Preception and Action, Halmstad, Schweden
• H. Speckmann, P. Thole, W. Rosenstiel
   Hardware Synthesis for Neural Networks from a Behavioural Description with VHDL
  IJCNN, Nagoya, Japan
• P. Gutberlet, W. Rosenstiel
   Interface Specification and Synthesis for VHDL Processes
  EURO-DAC, Paris, Frankreich
• P. Thole, U. Kebschull, W. Rosenstiel
   Klassische und High-Level-Synthese eines einfachen Mikroprozessors
  E.I.S.-Workshop, Tübingen
• J. Göppert, W. Rosenstiel
   Neuronale Netze: Revolutionierende Technik oder des Kaisers neue Kleider?
  Physik und Informatik in Wechselwirkung, Dresden
• J. Wedeck, W. Rosenstiel, C. Trautwein
   Optimierung und Parallelisierung von Programmen auf der Ebene von Flußgraphen
  ITG/GI
• H. Speckmann, W. Rosenstiel
   Parallele Implementierung Neuronaler Netze: Anforderungen und Vergleich
  E.I.S. Workshop, Tübingen
• E. Schubert, U. Kebschull, W. Rosenstiel
   Some Optimizations for Functional Decision Diagrams
  IFIP WG 10. 5 Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Interner Bericht Universität Tübingen, WSI-93-2, Hamburg
• W. Rosenstiel, U. Kebschull, T. Bubeck
   Sparrow - Ein Mikroprozessor-Entwurfs- und Ausbildungssystem
  Hochschul-Computer-Forum, Berlin
• P. Thole, H. Speckmann, W. Rosenstiel
   Synthesizing Hardware for Neural Networks with CADDY/CALLAS
  APCHDLSA, Queensland, Australien
• U. Weinmann, W. Rosenstiel
   Technology Mapping for Sequential Circuits based on Retiming Techniques
  EURO-DAC
• U. Kebschull, E. Schubert, P. Thole, W. Rosenstiel
   The Design and Implementation of an Educational Computer System Based on FPGAs
  Eurochip Workshop on VLSI Design Training, Toledo, Spanien
• E. Schubert, U. Kebschull, W. Rosenstiel
   The Use of FPGA for Educational Purposes in VLSI Microprocessor Design
  FPL-93, Oxford

Publikationen von 1992

• P. Gutberlet, J. Müller, H. Krämer, W. Rosenstiel
   Automatic Module Allocation in High Level Synthesis
  EURO-DAC, EURO-VHDL, p.328-333, Hamburg

• E. Barros, W. Rosenstiel
   A Method for Hardware Software Partitioning
  , p.580-585, Den Haag

• U. Kebschull, E. Schubert, W. Rosenstiel
   Multilevel Logic Synthesis Based on Functional Decision Diagrams
  EDAC, p.34-47, Brüssel, Belgien
• P. Gutberlet, W. Rosenstiel
   Scheduling Between Basic Blocks in the CADDY Synthesis System
  EDAC, p.496-500, Brüssel, Belgien

• J. Göppert, H. Speckmann, W. Rosenstiel, M. L. Kessler, U. Kraus, Gauglitz
   Evaluation of Spectra in Chemistry and Physics with Kohonen's Self-Organizing Feature Map
  NeuroNimes
• E. Schubert, U. Kebschull, W. Rosenstiel
   FDD Based Technology Mapping for FPGA
  EURO-ASIC, Paris
• H. Speckmann, P. Thole, W. Rosenstiel
   Hardware Implementation of Kohonen's Selforganizing Feature Map
  ICNN, IJCNN, Brighton, GB and Bejing, China
• P. Marwedel, W. Rosenstiel
   Synthese von Register-Transfer-Strukturen aus Verhaltensbeschreibungen
  Hauptbeitrag Informatik-Spektrum, Vol.15, p.5-22, Springer Verlag

Publikationen von 1991

• W. Rosenstiel, H. Krämer
   Scheduling and Assignment in High Level Synthesis Trends in High Level VLSI Synthesis
  , p.355-382, Kluwer Verlag, Boston, USA
• M. Rudolph, G. Neher, W. Rosenstiel
   Test Scheduling and Controller Synthesis in the CADDY-System
  EDAC, p.278-282, IEEE Computer Society Press

Publikationen von 1990

• H. Krämer, W. Rosenstiel
   Automatic Generation of Single Chip Multi Processor Systems
  IFIP Working Conference on Logic and Architecutre Synthesis, p.204-208, Paris
• P. Gutberlet, H. Krämer, W. Rosenstiel
   CASCH - ein Scheduling-Algorithmus für "High-Level"-Synthese
  Informatik Fachberichte, GME/GI/ITG-Fachtagung, Dortmund
• H. Krämer, W. Rosenstiel
   System Synthesis using Behavioural Descriptions
  EDAC, p.277-282, IEEE Computer Society Press

Publikationen von 1989

• O. Deussen, W. Rosenstiel, K. E. Schauser, J. Wedeck
   Architecture Design of a RISC-Processor for Prolog
  Microprocessing and Microprogramming, Vol.27, p.101-108, Holland
• T. Wecker, S. Kumar, W. Rosenstiel, H. Krämer, G. Neher
   CALLAS - ein System zur automatischen Synthese digitaler Schaltungen
  Informatik - Forschung und Entwicklung, p.37-54, Springer Verlag
• R. Amann, G. Neher, G. Rietsche, W. Rosenstiel
   CASTOR: FSM Synthesis in a Digital Circuit Synthesis System
  ESSCIRC, p.105-108
• P. Duzy, H. Krämer, G. Neher, M. Pilsl, W. Rosenstiel, T. Wecker
   Conversion of Algorithms to Library Adaptable Structures (CALLAS)
  VLSI, p.197-208
• W. Rosenstiel, R. Camposano
   Rechnergestützter Entwurf hochintegrierter MOS-Schaltungen
  Springer Verlag
• R. Camposano, W. Rosenstiel
   Synthesizing Circuits from Behavioural Level Specifications
  IEEE Transactions on Computer-Aided Design

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