A lot of research in the area of reconfigurable computing systems is focused on the re-use of devices for different applications. But compared to this, newly developed devices provide much more advantages. They allow to re-use the functional elements of a device for different operations within a single application. This is accomplished by extremely fast reconfiguration (in less than a clock cycle) during run-time. For these devices, frequent reconfiguration is part of the regular execution. The reconfiguration keeping pace with the execution yields an additional degree of freedom that constitutes a new principle of reconfiguration. We name this new principle processor-like reconfiguration. By means of reconfigurable data-paths, processor-like reconfiguration allows to instantiate and execute within one clock cycle exactly that part of a circuit that is needed in this cycle.

We investigate the advantages of processor-like reconfiguration compared to traditional processors as well as compared to conventional hardware solutions and in particular FPGAs. A major objective is to harness the advantages for applications. As a starting point for our research, we have defined the CRC model. the CRC model is a very general model for processor-like reconfigurable architectures that can be configured with a variety of parameters1. Based on that model we develop tools to build and benchmark such architectures, and to map applications onto them.

1 This configuration must not be confused with the reconfiguration of the architecture during run-time. These two different levels of (re-)configuration account for the name Configurable Reconfigurable Core (CRC).


Funded within SPP 1148