|
Organizer: Axel Braun, European SystemC User's Group & University of Tuebingen, DE
Description: The merger of the Open SystemC Initiative (OSCI) and Accellera to the Accellera Systems Initiative (ASI) unifies trend-setting standardization activities in the Electronic Design Automation (EDA) world and opens a wide range of new perspectives and synergies. The standards that are established and promoted by OSCI and Accellera cover a broad spectrum of today's and tomorrow's Electronic System Level (ESL) modeling and verification strategies. This workshop is focused on the core technologies from both the OSCI and the Accellera world, and gives an outlook on how techniques may collaborate and converge. The format of the workshop includes four invited sessions from Doulos, Synopsys, Cadence, and VWorks/ASTC Design providing a substantiated overview of the technologies and their future way providing a practical guide on how those technologies can be successfully applied for improving a companies design strategy. Five user sections from XMOS, Sonics and Lantiq, the University of Bremen, Bosch, and the Worcester Polytechnic Institute complement these core sections. They provide insights into the application and the development in research and industrial domains.
The programme is also available here. Room: Konferenz 4
The registration for this workshop will be handled within the registration for DATE conference: http://www.date-conference.com
We're looking forward to meeting you in Dresden!
Time | | Session |
---|
08:30
| | Welcome and Opening Axel Braun, University of Tuebingen & ESCUG, DE
| | | Core Section 1: Doulos IEEE 1666-2011 SystemC Standard John Aynsley, Doulos, U.K.
| 09:40 | | User Section 1: XMOS Using SystemC with XMOS Devices David Lacey, XMOS, U.K. | 10:10 | | Coffee Break | 10:30 | | Core Section 2: Synopsys TLM-2.0 Technology for Off-Chip Interfaces Victor Reyes, Synopsys, US | 11:30 | | User Section 2: Sonics and Lantiq SoC performance evaluation using high performance SystemQ and TLM models for communications SoCs Rocco Jonack, Sonics, US Bernhard Keppler, Lantiq, DE Renate Henftling, Lantiq, DE | 12:00 | | Lunch Break | 13:00 | | Core Section 3: Cadence Virtual Prototypes for Embedded Software Verification Markus Winterholer, Cadence, DE, Leonard Drucker, Cadence, US | 14:00 | | User Section 3: University of Bremen SystemC-based ESL Verification Flow Integrating Property Checking and Automatic Debugging Hoang M. Le, Daniel Grosse, Rolf Drechsler, University of Bremen and DFKI, DE | 14:30 | | Coffee Break | 14:50 | | +++ Please notice modification +++ Core Section 4: VWorks Programmable Debug of Linux/Android OS on Virtual PLatforms Jay Yantchev, VWorks, AU | 15:50 | | User Section 4: Bosch, Vienna University of Technology Using IP-XACT to ease system development with SystemC/TLM The Transparent TLM (TTLM) Approach Simon Hufnagel, Bosch, DE, Christoph Grimm, Vienna University of Technology, AT | 16:20 | | User Section 5: Worcester Polytechnic Institute System-Level Post-Manufacturing Testing Zainalabedin Navabi, Worcester Polytechnic Institute, US | 16:50 | | Closing Axel Braun, University of Tuebingen & ESCUG, DE |
|