Dr. Thomas Schweizer

Content

Publications

Publications

2016

Neues Konzept zur Steigerung der Zuverlaessigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs

by Konstantin Lübeck, David Morgenstern, Thomas Schweizer, Dustin Peterson, Wolfgang Rosenstiel, and Oliver Bringmann
In Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2016, 2016. [BIB]

@inproceedings{KDTDWO032016,
  author = {Lübeck, Konstantin and Morgenstern, David and Schweizer, Thomas and Peterson, Dustin and Rosenstiel, Wolfgang and Bringmann, Oliver},
  title = {Neues Konzept zur Steigerung der Zuverlaessigkeit einer ARM-basierten Prozessorarchitektur unter Verwendung eines CGRAs},
  booktitle = {Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2016},
  year = {2016},
  month = {mar},
  address = {Freiburg, Germany},
  month_numeric = {3}
}

Eine Tcl-basierte Methode zur Fehlerinjektion und Fehlereffektsimulation/-emulation auf Xilinx-FPGAs

by Thomas Schweizer, M. Simsek, Oliver Bringmann, and Wolfgang Rosenstiel
In Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2016, 2016. [BIB]

@inproceedings{TMOW032016,
  author = {Schweizer, Thomas and Simsek, M. and Bringmann, Oliver and Rosenstiel, Wolfgang},
  title = {Eine Tcl-basierte Methode zur Fehlerinjektion und Fehlereffektsimulation/-emulation auf Xilinx-FPGAs},
  booktitle = {Proceedings Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV) Workshop 2016},
  year = {2016},
  month = {mar},
  address = {Freiburg, Germany},
  month_numeric = {3}
}

2013

Testing Reliability Techniques for SoCs with Fault Tolerant CGRA by using live FPGA Fault Injection

by J. M. Kühn, Thomas Schweizer, Dustin Peterson, Tommy Kuhn, and Wolfgang Rosenstiel
In Proceeding of the International Conference on Field Programmable Technology (ICFPT), Kyoto, Japan, 2013. [BIB]

@inproceedings{JTDTW122013,
  author = {Kühn, J. M. and Schweizer, Thomas and Peterson, Dustin and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Testing Reliability Techniques for SoCs with Fault Tolerant CGRA by using live FPGA Fault Injection},
  booktitle = {Proceeding of the International Conference on Field Programmable Technology (ICFPT), Kyoto, Japan},
  year = {2013},
  month = {dec},
  month_numeric = {12}
}

StML: Bridging the Gap between FPGA Design and HDL Circuit Description

by Dustin Peterson, Thomas Schweizer, Oliver Bringmann, and Wolfgang Rosenstiel
In Proceeding of the International Conference on Field Programmable Technology (ICFPT), Kyoto, Japan, 2013. [BIB]

@inproceedings{DTOW122013,
  author = {Peterson, Dustin and Schweizer, Thomas and Bringmann, Oliver and Rosenstiel, Wolfgang},
  title = {StML: Bridging the Gap between FPGA Design and HDL Circuit Description},
  booktitle = {Proceeding of the International Conference on Field Programmable Technology (ICFPT), Kyoto, Japan},
  year = {2013},
  month = {dec},
  month_numeric = {12}
}

2012

Improving System Reliability using Dynamic Functional Verification on CGRAs

by J. M. Kühn, Sven Eisenhardt, Thomas Schweizer, Tommy Kuhn, and Wolfgang Rosenstiel
In Proceedings of the International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), 2012. [BIB]

@inproceedings{JMSTTW062012,
  author = {Kühn, J. M. and Eisenhardt, Sven and Schweizer, Thomas and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Improving System Reliability using Dynamic Functional Verification on CGRAs},
  booktitle = {Proceedings of the International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART)},
  year = {2012},
  month = {jun},
  address = {Okinawa, Japan},
  month_numeric = {6}
}

Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable Architectures

by Thomas Schweizer, A. Kuester, Sven Eisenhardt, Tommy Kuhn, and Wolfgang Rosenstiel
In International Parellel and Distributed Processing Symposium Workshops (IPDPSW), 2012. [BIB]

@inproceedings{TASTW052012,
  author = {Schweizer, Thomas and Kuester, A. and Eisenhardt, Sven and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable Architectures},
  booktitle = {International Parellel and Distributed Processing Symposium Workshops (IPDPSW)},
  year = {2012},
  month = {may},
  address = {Shanghai, China},
  organization = {IEEE},
  month_numeric = {5}
}

2011

Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures

by Thomas Schweizer, P. Schlicker, Sven Eisenhardt, Tommy Kuhn, and Wolfgang Rosenstiel
In International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2011. [BIB]

@inproceedings{TPSTW112011,
  author = {Schweizer, Thomas and Schlicker, P. and Eisenhardt, Sven and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable Architectures},
  booktitle = {International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
  year = {2011},
  month = {nov},
  address = {Cancun, Mexico},
  organization = {IEEE},
  month_numeric = {11}
}

Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures

by Sven Eisenhardt, A. Küster, Thomas Schweizer, Tommy Kuhn, and Wolfgang Rosenstiel
In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2011. [BIB]

@inproceedings{SATTW102011,
  author = {Eisenhardt, Sven and Küster, A. and Schweizer, Thomas and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures},
  booktitle = {IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)},
  year = {2011},
  month = {oct},
  address = {Vancouver, Canada},
  month_numeric = {10}
}

Runtime Datapath Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures

by Sven Eisenhardt, A. Küster, Thomas Schweizer, Tommy Kuhn, and Wolfgang Rosenstiel
In International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC). IEEE, 2011. [BIB]

@inproceedings{SATTW062011,
  author = {Eisenhardt, Sven and Küster, A. and Schweizer, Thomas and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Runtime Datapath Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures},
  booktitle = {International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)},
  publisher = {IEEE},
  year = {2011},
  month = {jun},
  address = {Montpellier, Frankreich},
  month_numeric = {6}
}

2010

Charge Recycling in Voltage-Dithered Circuits

by Thomas Schweizer, J. Oliveira, Tommy Kuhn, and Wolfgang Rosenstiel
In Journal of Low Power Electronics, 2010. [BIB]

@inproceedings{TJTW082010,
  author = {Schweizer, Thomas and Oliveira, J. and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Charge Recycling in Voltage-Dithered Circuits},
  booktitle = {Journal of Low Power Electronics},
  year = {2010},
  month = {aug},
  month_numeric = {8}
}

Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications: Evaluation and Design Methods for Processor-Like Reconfigurable Architectures

by Sven Eisenhardt, Thomas Schweizer, J. Oliveira, Tommy Kuhn, and Wolfgang Rosenstiel
, pages 95ff. Springer, 2010. [BIB]

@book{STJTW022010,
  author = {Eisenhardt, Sven and Schweizer, Thomas and Oliveira, J. and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications: Evaluation and Design Methods for Processor-Like Reconfigurable Architectures },
  publisher = {Springer},
  year = {2010},
  month = {feb},
  pages = {95ff},
  month_numeric = {2}
}

2009

Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures

by Sven Eisenhardt, Thomas Schweizer, Andreas Bernauer, Tommy Kuhn, and Wolfgang Rosenstiel
In International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2009. [BIB]

@inproceedings{STATW122009,
  author = {Eisenhardt, Sven and Schweizer, Thomas and Bernauer, Andreas and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures},
  booktitle = {International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
  publisher = {IEEE},
  year = {2009},
  month = {dec},
  address = {Cancun, Mexico},
  month_numeric = {12}
}

CGADL: an Architecture Description Language for Coarse-Grained Reconfigurable Arrays

by Julio Alexandrino de Oliveira Filho, S. Masekowsky, Thomas Schweizer, and Wolfgang Rosenstiel
In IEEE Transactions in Very Large Scale Integration Systems, 2009. [BIB]

@inproceedings{JSTW092009,
  author = {de Oliveira Filho, Julio Alexandrino and Masekowsky, S. and Schweizer, Thomas and Rosenstiel, Wolfgang},
  title = {CGADL: an Architecture Description Language for Coarse-Grained Reconfigurable Arrays},
  booktitle = {IEEE Transactions in Very Large Scale Integration Systems},
  year = {2009},
  month = {sep},
  month_numeric = {9}
}

2008

Optimizing Partial Reconfiguration of Multi-Context Architectures

by Sven Eisenhardt, Tobias Oppold, Thomas Schweizer, and Wolfgang Rosenstiel
In International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE, 2008. [BIB]

@inproceedings{STTW122008,
  author = {Eisenhardt, Sven and Oppold, Tobias and Schweizer, Thomas and Rosenstiel, Wolfgang},
  title = {Optimizing Partial Reconfiguration of Multi-Context Architectures},
  booktitle = {International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
  publisher = {IEEE},
  year = {2008},
  month = {dec},
  address = {Cancun, Mexico},
  month_numeric = {12}
}

2007

An Architecture Description Language for coarse-grained Reconfigurable Arrays

by Julio Alexandrino de Oliveira Filho, S. Masekowsky, Thomas Schweizer, and Wolfgang Rosenstiel
In International Conference on Hardware/Software Codesign and System Synthesis (CODES) - Workshop on Application Specific Processors (WASP), 2007. [BIB]

@inproceedings{JOSTW102007,
  author = {de Oliveira Filho, Julio Alexandrino and Masekowsky, S. and Schweizer, Thomas and Rosenstiel, Wolfgang},
  title = {An Architecture Description Language for coarse-grained Reconfigurable Arrays},
  booktitle = {International Conference on Hardware/Software Codesign and System Synthesis (CODES) - Workshop on Application Specific Processors (WASP)},
  year = {2007},
  month = {oct},
  address = {Salzburg, Austria},
  month_numeric = {10}
}

Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures

by Thomas Schweizer, Tobias Oppold, Julio Alexandrino de Oliveira Filho, Sven Eisenhardt, K. Blocher, and Wolfgang Rosenstiel
In International Conference on Field Programmable Technology (ICFPT), 2007. [BIB]

@inproceedings{TTJOSKW2007,
  author = {Schweizer, Thomas and Oppold, Tobias and de Oliveira Filho, Julio Alexandrino and Eisenhardt, Sven and Blocher, K. and Rosenstiel, Wolfgang},
  title = {Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures},
  booktitle = {International Conference on Field Programmable Technology (ICFPT)},
  year = {2007},
  address = {Kitakyushu, Japan}
}

Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable Architecture

by M. Rullmann, S. Siegel, R. Merker, Julio Alexandrino de Oliveira Filho, Thomas Schweizer, Tobias Oppold, and Wolfgang Rosenstiel
In 20. International Conference on Architecture of Computing Systems (ARCS), Workshop on Dynamically Reconfigurable Systems (DRS), 2007. [BIB]

@inproceedings{MSRJOTTW2007,
  author = {Rullmann, M. and Siegel, S. and Merker, R. and de Oliveira Filho, Julio Alexandrino and Schweizer, Thomas and Oppold, Tobias and Rosenstiel, Wolfgang},
  title = {Efficient Mapping and Functional Verification of Parallel Algorithms on a Multi-Context Reconfigurable Architecture},
  booktitle = {20. International Conference on Architecture of Computing Systems (ARCS), Workshop on Dynamically Reconfigurable Systems (DRS)},
  year = {2007},
  address = { Zürich, Schweiz}
}

CRC - Concepts and Evaluation of Processor-Like Reconfigurable Archtitectures

by Tobias Oppold, Thomas Schweizer, J. F. Oliveira, Sven Eisenhardt, and Wolfgang Rosenstiel
In it - Information Technology, DOI: 10. 1524/itit, 49. 3. 157 49(3), 2007. [BIB]

@inproceedings{TTJFSW2007,
  author = {Oppold, Tobias and Schweizer, Thomas and Oliveira, J. F. and Eisenhardt, Sven and Rosenstiel, Wolfgang},
  title = {CRC - Concepts and Evaluation of Processor-Like Reconfigurable Archtitectures},
  booktitle = {it - Information Technology, DOI: 10. 1524/itit, 49. 3. 157},
  year = {2007},
  volume = {49},
  number = {3}
}

2006

Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain

by Julio Alexandrino de Oliveira Filho, Thomas Schweizer, Tobias Oppold, Tommy Kuhn, and Wolfgang Rosenstiel
In 3. International Conference on Reconfigurable Computing and FPGAs (ReConfig), pages 71-77, 2006. [BIB]

@inproceedings{JOTTTW092006,
  author = {de Oliveira Filho, Julio Alexandrino and Schweizer, Thomas and Oppold, Tobias and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain},
  booktitle = {3. International Conference on Reconfigurable Computing and FPGAs (ReConfig)},
  year = {2006},
  month = {sep},
  pages = {71-77},
  address = {San Luis Potosi, Mexiko},
  month_numeric = {9}
}

Execution Schemes for Dynamically Reconfigurable Architectures

by Tobias Oppold, Thomas Schweizer, J. F. Oliveira, Sven Eisenhardt, Tommy Kuhn, and Wolfgang Rosenstiel
In Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), 2006. [BIB]

@inproceedings{TTJFSTW2006,
  author = {Oppold, Tobias and Schweizer, Thomas and Oliveira, J. F. and Eisenhardt, Sven and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Execution Schemes for Dynamically Reconfigurable Architectures},
  booktitle = {Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)},
  year = {2006},
  address = {Nagoya, Japan}
}

2005

Evaluation of Temporal-Spatial Voltage Scaling for Processor-Like Reconfigurable Architectures

by Thomas Schweizer, J. F. Oliveira, Tobias Oppold, Tommy Kuhn, and Wolfgang Rosenstiel
In Euro DesignCon, 2005. [BIB]

@inproceedings{TJFTTW2005,
  author = {Schweizer, Thomas and Oliveira, J. F. and Oppold, Tobias and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Evaluation of Temporal-Spatial Voltage Scaling for Processor-Like Reconfigurable Architectures},
  booktitle = {Euro DesignCon},
  year = {2005},
  address = {Munich, Germany}
}

Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures

by Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel, U. Kanus, and W. Straßer
In International Conference on Field Programmable Logic and Applications (FPL), 2005. [BIB]

@inproceedings{TTTWUW2005,
  author = {Oppold, Tobias and Schweizer, Thomas and Kuhn, Tommy and Rosenstiel, Wolfgang and Kanus, U. and Straßer, W.},
  title = {Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures},
  booktitle = {International Conference on Field Programmable Logic and Applications (FPL)},
  year = {2005},
  address = {Tampere, Finland}
}

2004

Object-Oriented Modeling and Synthesis of SystemC Specifications

by C. Schulz-Key, Markus Winterholer, Thomas Schweizer, Tommy Kuhn, and Wolfgang Rosenstiel
In Asia South Pacific Design Automation Conference (ASPDAC), 2004. [BIB]

@inproceedings{CMTTW2004,
  author = {Schulz-Key, C. and Winterholer, Markus and Schweizer, Thomas and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Object-Oriented Modeling and Synthesis of SystemC Specifications},
  booktitle = {Asia South Pacific Design Automation Conference (ASPDAC)},
  year = {2004},
  address = {Yokohama, Japan}
}

Object-Oriented Hardware Synthesis with SystemC

by Markus Winterholer, C. Schulz-Key, Thomas Schweizer, Tommy Kuhn, and Wolfgang Rosenstiel
In In Proceedings of Forum on Design Languages (FDL), 2004. [BIB]

@inproceedings{MCTTW2004,
  author = {Winterholer, Markus and Schulz-Key, C. and Schweizer, Thomas and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Object-Oriented Hardware Synthesis with SystemC},
  booktitle = {In Proceedings of Forum on Design Languages (FDL)},
  year = {2004}
}

Cost Functions for the Design of Dynamically Reconfigurable Processor Architectures

by Tobias Oppold, Thomas Schweizer, Tommy Kuhn, and Wolfgang Rosenstiel
In Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), 2004. [BIB]

@inproceedings{TTTW2006,
  author = {Oppold, Tobias and Schweizer, Thomas and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {Cost Functions for the Design of Dynamically Reconfigurable Processor Architectures},
  booktitle = {Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI)},
  year = {2004},
  address = {Kanazawa, Japan}
}

A New Design Approach for Processor-Like Reconfigurable Hardware

by Tobias Oppold, Thomas Schweizer, Tommy Kuhn, and Wolfgang Rosenstiel
In Euro DesignCon, 2004. [BIB]

@inproceedings{TTTW2005,
  author = {Oppold, Tobias and Schweizer, Thomas and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {A New Design Approach for Processor-Like Reconfigurable Hardware},
  booktitle = {Euro DesignCon},
  year = {2004},
  address = {München}
}

A Design Environment for Processor-Like Reconfigurable Hardware

by Tobias Oppold, Thomas Schweizer, Tommy Kuhn, and Wolfgang Rosenstiel
In IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC), 2004. [BIB]

@inproceedings{TTTW2004,
  author = {Oppold, Tobias and Schweizer, Thomas and Kuhn, Tommy and Rosenstiel, Wolfgang},
  title = {A Design Environment for Processor-Like Reconfigurable Hardware},
  booktitle = {IEEE International Conference on Parallel Computing in Electrical Engineering (PARELEC)},
  year = {2004},
  address = {Dresden, Germany}
}